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PDF CY7C1049B Data sheet ( Hoja de datos )

Número de pieza CY7C1049B
Descripción 512K x 8 Static RAM
Fabricantes Cypress Semiconductor 
Logotipo Cypress Semiconductor Logotipo



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No Preview Available ! CY7C1049B Hoja de datos, Descripción, Manual

049B
CY7C1049B
512K x 8 Static RAM
Features
• High speed
— tAA = 12 ns
• Low active power
— 1320 mW (max.)
• Low CMOS standby power (Commercial L version)
— 2.75 mW (max.)
www.DataSheet4U2.c.0oVm Data Retention (400 µW at 2.0V retention)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
Functional Description[1]
The CY7C1049B is a high-performance CMOS static RAM or-
ganized as 524,288 words by 8 bits. Easy memory expansion
Logic Block Diagram
is provided by an active LOW Chip Enable (CE), an active
LOW Output Enable (OE), and three-state drivers. Writing to
the device is accomplished by taking Chip Enable (CE) and
Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0
through I/O7) is then written into the location specified on the
address pins (A0 through A18).
Reading from the device is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1049B is available in a standard 400-mil-wide
36-pin SOJ package with center power and ground (revolu-
tionary) pinout.
Pin Configuration
SOJ
Top View
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
CE
WE
INPUT BUFFER
512K x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
A0
A1
A2
A3
A4
CE
I/O0
I/O1
VCC
GND
I/O2
I/O3
WE
A5
A6
A7
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36 NC
35 A18
34 A17
33 A16
32 A15
31 OE
30 I/O7
29 I/O6
28 GND
27 VCC
26 I/O5
25 I/O4
24 A14
23 A13
22 A12
21 A11
20 A10
19 NC
OE
Selection Guide
7C1049B-12 7C1049B-15 7C1049B-17 7C1049B-20 7C1049B-25
Maximum Access Time (ns)
12 15
17 20
25
Maximum Operating Current (mA)
240 220 195 185 180
Maximum CMOS Standby
Current (mA)
Coml
Coml/Indl L
8
-
888 8
-
0.5 0.5
0.5
Indl - - - 9 9
Note:
1. For guidelines on SRAM system design, please refer to the System Design GuidelinesCypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05169 Rev. *A
Revised September 13, 2002

1 page




CY7C1049B pdf
CY7C1049B
Switching Characteristics[4] Over the Operating Range (continued)
Parameter
Description
Read Cycle
tpower
VCC(typical) to the First Access[5]
tRC Read Cycle Time
tAA Address to Data Valid
tOHA
Data Hold from Address Change
tACE CE LOW to Data Valid
www.DataSheett4DUO.Ecom
tLZOE
tHZOE
tLZCE
tHZCE
OE LOW to Data Valid
OE LOW to Low Z[7]
OE HIGH to High Z[6, 7]
CE LOW to Low Z[7]
CE HIGH to High Z[6, 7]
tPU CE LOW to Power-Up
tPD CE HIGH to Power-Down
Write Cycle[8]
tWC
tSCE
tAW
tHA
tSA
tPWE
tSD
tHD
tLZWE
tHZWE
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z[7]
WE LOW to High Z[6, 7]
7C1049B-20
Min.
Max.
1
20
20
3
20
8
0
8
3
8
0
20
20
13
13
0
0
13
9
0
3
8
7C1049B-25
Min.
Max.
Unit
11
25 ns
25 ns
5 ns
25 ns
10 ns
0 ns
10 ns
5 ns
10 ns
0 ns
25 ns
25 ns
15 ns
15 ns
0 ns
0 ns
15 ns
10 ns
0 ns
5 ns
10 ns
Data Retention Characteristics Over the Operating Range
Parameter
Description
Conditions[11]
VDR VCC for Data Retention
ICCDR
Data Retention Current
Coml L
Indl
tCDR[3]
tR[10]
Chip Deselect to Data Retention Time
Operation Recovery Time
Notes:
10. tr < 3 ns for the -12 and -15 speeds. tr < 5 ns for the -20 ns and slower speeds.
11. No input may exceed VCC + 0.5V.
VCC = VDR = 3.0V,
CE > VCC 0.3V
VIN > VCC 0.3V or VIN < 0.3V
Min.
2.0
0
tRC
Max
200
1
Unit
V
µA
mA
ns
ns
Document #: 38-05169 Rev. *A
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