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PDF STF4A60S Data sheet ( Hoja de datos )

Número de pieza STF4A60S
Descripción Sensitive Gate Triacs
Fabricantes SemiWell Semiconductor 
Logotipo SemiWell Semiconductor Logotipo



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No Preview Available ! STF4A60S Hoja de datos, Descripción, Manual

SemiWell Semiconductor
Sensitive Gate Triacs
Features
Repetitive Peak Off-State Voltage : 600V
R.M.S On-State Current ( IT(RMS)= 4 A )
High Commutation dv/dt
Sensitive Gate Triggering 4 Mode
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General Description
This device is sensitive gate triac suitable for direct coupling
to TTL, HTL, CMOS and application such as various logic
functions, low power AC switching applications, such as fan
speed, small light controllers and home appliance equipment.
STF4A60S
Symbol
2.T2
▼▲
3.Gate
1.T1
TO-220F
1
2
3
Absolute Maximum Ratings ( TJ = 25°C unless otherwise specified )
Symbol
Parameter
Condition
VDRM
IT(RMS)
ITSM
I2t
Repetitive Peak Off-State Voltage
R.M.S On-State Current
Surge On-State Current
I2t for Fusing
Sine wave, 50 to 60 Hz, Gate open
TC = 99 °C, Full Sine wave
One Cycle, 50Hz/60Hz, Peak,
Non-Repetitive
tp = 10ms
PGM
PG(AV)
IGM
VGM
TJ
TSTG
Peak Gate Power Dissipation
Average Gate Power Dissipation
Peak Gate Current
Peak Gate Voltage
Operating Junction Temperature
Storage Temperature
Mass
TC = 99 °C, Pulse width 1.0us
Over any 20ms period
tp = 20us, TJ=125°C
tp = 20us, TJ=125°C
Ratings
600
4.0
30/33
4.5
3
0.3
1.0
7.0
- 40 ~ 125
- 40 ~ 150
2.0
Units
V
A
A
A2s
W
W
A
V
°C
°C
g
Aug, 2004. Rev.1
copyright@SemiWell Semiconductor Co., Ltd., All rights reserved.
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1 page




STF4A60S pdf
STF4A60S
TO-220F Package Dimension
Dim.
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A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
φ
φ1
φ2
Min.
10.4
6.18
9.55
13.47
6.05
1.26
3.17
1.87
2.57
2.51
1.25
0.45
0.6
mm
Typ.
2.54
5.08
3.7
3.2
1.5
Max.
10.6
6.44
9.81
13.73
6.15
1.36
3.43
2.13
2.83
2.62
1.55
0.63
1.0
Min.
0.409
0.243
0.376
0.530
0.238
0.050
0.125
0.074
0.101
0.099
0.049
0.018
0.024
Inch
Typ.
0.100
0.200
0.146
0.126
0.059
Max.
0.417
0.254
0.386
0.540
0.242
0.054
0.135
0.084
0.111
0.103
0.061
0.025
0.039
F
B
A
E
HI
φ
C
G
D
L
1
2
3
J
K
N
φ1
φ2
M
O
1. T1
2. T2
3. Gate
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