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PDF DP80390XP Data sheet ( Hoja de datos )
| Número de pieza | DP80390XP | |
| Descripción | Pipelined High Performance 8-bit Microcontroller | |
| Fabricantes | Digital Core Design | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de DP80390XP (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
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DP80390XP
Pipelined High Performance
8-bit Microcontroller
ver 3.10
OVERVIEW
DP80390XP is an ultra high perform-
ance, speed optimized soft core of a single-
chip 8-bit embedded controller dedicated for
operation with fast (typically on-chip) and slow
(off-chip) memories. The core has been de-
signed with a special concern about perform-
ance to power consumption ratio. This ratio
is extended by an advanced power manage-
ment unit PMU.
DP80390XP soft core is 100% binary-
compatible with the industry standard 80390 &
8051 8-bit microcontroller. There are two con-
figurations of DP80390XP: Harward where
internal data and program buses are sepa-
rated, and von Neumann with common pro-
gram and external data bus. DP80390XP has
Pipelined RISC architecture 10 times faster
compared to standard architecture and exe-
cutes 85-200 million instructions per second.
This performance can also be exploited to
great advantage in low power applications
where the core can be clocked over ten times
more slowly than the original implementation
for no performance penalty.
DP80390XP is fully customizable, which
means it is delivered in the exact configuration
to meet users’ requirements. There is no need
to pay extra for not used features and wasted
silicon. It includes fully automated testbench
with complete set of tests allowing easy
package validation at each stage of SoC de-
sign flow.
CPU FEATURES
● 100% software compatible with industry
standard 80390 & 8051
○ LARGE mode – 8051 instruction set
○ FLAT mode – 80390 instruction set
● Pipelined RISC architecture enables to
execute instructions 10 times faster com-
pared to standard 8051
● 24 times faster multiplication
● 12 times faster addition
● 2 Data Pointers (DPTR) for faster memory
blocks copying
○ Advanced INC & DEC modes
○ Auto-switch of current DPTR
● Up to 256 bytes of internal (on-chip) Data
Memory
● Up to 16M bytes of linear Program
Memory
○ 64 kB of internal (on-chip) Program Memory
○ 16 MB external (off-chip) Program Memory
● Up to 16M bytes of external (off-chip) Data
Memory
● User programmable Program Memory Wait
States solution for wide range of memories
speed
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved.
1 page  
SYMBOL
BLOCK DIAGRAM
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clk
reset
ramdatai(7:0)
sfrdatai(7:0)
ramdatao(7:0)
ramaddr(7:0)
ramoe
ramwe
sfrdatao(7:0)
sfraddr(7:0)
sfroe
sfrwe
prgromdatai(7:0) prgdatao(7:0)
prgramdatai(7:0) prgaddr(15:0)
prgramwr
xdatai(7:0)
ready
iprgromsize(2:0)
iprgramsize(2:0)
xdatao(7:0)
xaddr(23:0)
xdataz
xdatard
xdatawr
xprgrd
xprgwr
int0
int1
int2
int3
int4
int5
int6
docddatai
port0i(7:0)
port1i(7:0)
port2i(7:0)
port3i(7:0)
docddatao
docdclk
stop
pmm
port0o(7:0)
port1o(7:0)
port2o(7:0)
port3o(7:0)
t0
gate0
t1
gate1
t2
t2ex
capture0
capture1
capture2
capture3
rxd0i
rxd1i
mscli
msdai
rxd0o
txd0
rxd1o
txd1
msclhs
msclo
msdao
sscli
ssdai
ss
si
mi
scki
ssclo
ssdao
sso(7:0)
so
mo
scko
sckz
clk
reset
prgromdatai(7:0)
prgramdatai(7:0)
prgdatao(7:0)
prgaddr(15:0)
prgramwr
xdatai(7:0)
xdatao(7:0)
xramaddr(23:0)
xramdataz
xdatard
xdatawr
xprgrd
xprgwr
ready
ramdatai(7:0)
ramdatao(7:0)
ramaddr(7:0)
ramoe
ramwe
sfrdatai(7:0)
sfrdatao(7:0)
sfraddr(7:0)
sfroe
sfrwe
docddatai
docddatao
docdclk
Opcode
Decoder
Program
Memory
Interface
External
Memory
Interface
Internal Data
Memory
Interface
User SFR
Interface
DoCD™
Debug Unit
Floating
Point Unit
t2
t2ex
Timer 2
capture0
capture1
capture2
capture3
rxd1o
rxd1i
txd1
msclhs
mscli
msclo
msdai
msdao
sscli
ssclo
ssdai
ssdao
Compare
Capture Unit
UART 1
Master
I2C Unit
Slave
I2C Unit
ALU
Control Unit
iprgromsize(2:0)
iprgramsize(2:0)
Interrupt
Controller
I/O Ports
int0
int1
int2
int3
int4
int5
int6
port0i(7:0)
port1i(7:0)
port2i(7:0)
port3i(7:0)
port0o(7:0)
port1o(7:0)
port2o(7:0)
port3o(7:0)
Power
Management
Unit
stop
pmm
Multiply
Divide Unit
Timers 0 & 1
t0
gate0
t1
gate1
Watchdog
Timer
UART 0
SPI Unit
rxd0o
rxd0i
txd0
so
si
mo
mi
scko
scki
sckz
ss
sso(7:0)
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved.
5 Page 
The main features of each DP80390 family member have been summarized in table below. It gives
a briefly member characterization helping user to select the most suitable IP Core for its application.
User can specify its own peripheral set (including listed below and the others) and requests the core
modifications.
Design
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Program
Memory
space
DP80390CPU 10 64k 64k 16M 256 256 16M
DP80390
10 64k 64k 16M 256 256 16M
DP80390XP 10 64k 64k 16M 256 256 16M
221 - - - - - - - - - -
521214 - - - - - - -
15 2 2 3 2 4
DP80390 family of Pipelined High Performance Microcontroller Cores
The main features of each DP8051 family member have been summarized in table below. It gives
a briefly member characterization helping user to select the most suitable IP Core for its application.
User can specify its own peripheral set (including listed below and the others) and requests the core
modifications.
Design
Program
Memory
space
DP8051CPU
DP8051
DP8051XP
10 64k 64k 64k 256 256 16M
10 64k 64k 64k 256 256 16M
10 64k 64k 64k 256 256 16M
221 - - - - - - - - - -
521214 - - - - - - -
15 2 2 3 2 4
DP8051 family of Pipelined High Performance Microcontroller Cores
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved.
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet DP80390XP.PDF ] | |
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