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PDF HYI39S512400A Data sheet ( Hoja de datos )
| Número de pieza | HYI39S512400A | |
| Descripción | 512-Mbit Synchronous DRAM | |
| Fabricantes | Qimonda | |
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HY[B/I]39S512400A[E/T]
HY[B/I]39S512800A[E/T]
HY[B/I]39S512160A[E/T]
www.DataSheet4U.com
512-Mbit Synchronous DRAM
SDRAM
RoHS Compliant Products
June 2007
Internet Data Sheet
Rev. 1.52
1 page  
Internet Data Sheet
2 Configuration
HY[I/B]39S512[40/80/16]0A[E/T]
512-Mbit Synchronous DRAM
This chapter contains the pin configuration table and the TSOP package drawing.
2.1www.DataSheet4U.com
Pin Configuration
Listed below are the pin configurations sections for the various signals of the SDRAM.
TABLE 3
Ball Configuration of the SDRAM
Ball No. Name Pin Buffer
Type Type
Function
Clock Signals x4/ x8/ x16 Organization
38
CLK I
LVTTL Clock Signal CLK
37
CKE I
LVTTL Clock Enable
Control Signals x4/ x8/ x16 Organization
18
RAS I
LVTTL Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE)
17
CAS I
LVTTL
16
WE I
LVTTL
19
CS I
LVTTL Chip Select
Address Signals x4/ x8/ x16 Organization
20
BA0 I
LVTTL Bank Address Signals 1:0
21
BA1 I
LVTTL
23
A0 I
LVTTL Address Signal 9:0, Address Signal 10/Auto precharge
24
A1 I
LVTTL
25
A2 I
LVTTL
26
A3 I
LVTTL
29
A4 I
LVTTL
30
A5 I
LVTTL
31
A6 I
LVTTL
32
A7 I
LVTTL
33
A8 I
LVTTL
34
A9 I
LVTTL
22
A10 I
LVTTL
35
A11 I
LVTTL
36
A12 I
LVTTL
Rev. 1.52, 2007-06
03292006-6Y91-0T2Z
5
5 Page 
Internet Data Sheet
HY[I/B]39S512[40/80/16]0A[E/T]
512-Mbit Synchronous DRAM
Burst Length
www.DataShee2t4U.com
4
8
FullPage
Starting Column Address
A2 A1
0
0
1
1
00
00
01
01
10
10
11
11
n
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
TABLE 6
Burst Length and Sequence
Order of Accesses Within a Burst
Type=Sequential
0–1
1–0
0–1–2–3
1–2–3–0
2–3–0–1
3–0–1–2
0–1–2–3–4–5–6–7
1–2–3–4–5–6–7–0
2–3–4–5–6–7–0–1
3–4–5–6–7–0–1–2
4–5–6–7–0–1–2–3
5–6–7–0–1–2–3–4
6–7–0–1–2–3–4–5
7–0–1–2–3–4–5–6
Cn, Cn+1, Cn+2 ....
Type=Interleaved
0–1
1–0
0–1–2–3
1–0–3–2
2–3–0–1
3–2–1–0
0–1–2–3–4–5–6–7
1–0–3–2–5–4–7–6
2–3–0–1–6–7–4–5
3–2–1–0–7–6–5–4
4–5–6–7–0–1–2–3
5–4–7–6–1–0–3–2
6–7–4–5–2–3–0–1
7–6–5–4–3–2–1–0
Not supported
Notes
1. For a burst length of two, A1-Ai selects the two-data-element block; A0 selects the first access within the block.
2. For a burst length of four, A2-Ai selects the four-data-element block; A0-A1 selects the first access within the block.
3. For a burst length of eight, A3-Ai selects the eight-data- element block; A0-A2 selects the first access with in the block.
4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.
Rev. 1.52, 2007-06
03292006-6Y91-0T2Z
11
11 Page | ||
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