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PDF RT8801B Data sheet ( Hoja de datos )
| Número de pieza | RT8801B | |
| Descripción | Multi-Phase PWM Controller | |
| Fabricantes | Richtek Technology | |
| Logotipo |  |
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Preliminary
RT8801B
Multi-Phase PWM Controller for K8 CPU Core Power
Supply with Serial Programming Interface
General Description
The RT8801B is a multi-phase synchronous buck controller
which is implemented with full control functions for AMD
K8 compliant CPU. The RT8801B could be operated with
2, 3 or 4 buck switching stages operating in interleaved
phase set automatically. The multiphase architecture
www.DataSpheroetv4iUd.ecsomhigh output current while maintaining low power
dissipation on power devices and low stress on input and
output capacitors.
RT8801B is one of RichTek CPU core power solutions
which integrates a specific series programming interface
for the controller peration configuration. There are several
registers implemented for the specific parameters
configuration including VID for core power, and signal for
load current indication. User can program the configuration
of the parameters easily via the specific programming
interface. With the implementation of RT8801B, the part
provides more flexibility and feature for customers advanced
segment product design.
The RT8801B applies the DCR sensing technology newly
as well; with such a topology, the RT8801B extracts the
DCR of output inductor as sense component to deliver a
more precise load line regulation and better thermal
balance for next generation processor application. For
current sense setting, droop tuning, VCORE initial offset
and over current protection are independent to
compensation circuit of voltage loop. The feature greatly
facilitates the flexibility of CPU power supply design and
tuning. The DAC output of RT8801B supports AMD CPU
with 6-bit VID input, precise initial value & smooth VCORE
transient at VID jump. The IC monitors the VCORE voltage
for over-voltage protection. Soft-start, over-current
protection and programmable under-voltage lockout are
also provided to assure the safety of microprocessor and
power system. The RT8801B comes to the package of
VQFN-32L 5x5.
Features
z Multi-Phase Power Conversion with Automatic
Phase Selection
z 6-bits AMD K8 DAC Output with Active Droop
Compensation for Fast Load Transient
z Smooth VCORE Transition at VID Jump
z Power Stage Thermal Balance by DCR Current
Sense
z Hiccup Mode Over-Current Protection
z Adjustable Switching Frequency (50kHz to 400kHz
per Phase)
z Under-Voltage Lockout and Soft-Start
z High Ripple Frequency Times Channel Number
z 2-Wires Programming Interface
z Software Programmable VID
z 32-Lead VQFN Package
z RoHS Compliant and 100% Lead (Pb)-Free
Applications
z AMD K8 compliant Processors Voltage Regulator
z Low Output Voltage, High power density DC-DC
Converters
z Voltage Regulator Modules
Ordering Information
RT8801B
Package Type
QV : VQFN-32L 5x5 (V-Type)
Operating Temperature Range
P : Pb Free with Commercial Standard
G : Green (Halogen Free with Commer-
cial Standard)
Note :
Richtek Pb-free and Green products are :
`RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
`Suitable for use in SnPb or Pb-free soldering processes.
`100% matte tin (Sn) plating.
DS8801B-04 August 2007
All brandname or trademark belong to their owner respectively
www.richtek.com
1
1 page  
Preliminary
RT8801B
Functional Pin Description
SLOT_OCC (Pin 1)
CPU socket occupied; the signal is defined to indicate if
the CPU has been changed/ removed and it will reset all
chip. There is one register implemented for the status
indication. The register will be reset when the VDD power
removed or CPU changed/removed. The pin is
implemented as an input, TTL level, and active-low signal.
pin; the internal trip threshold = 0.9V at VDVD rising.
SS (Pin 13)
The pin is defined to set soft-start ramp rate; a capacitor
is attached to set the start time interval. Pull this pin lower
than 1.0V (ramp valley of saw-tooth wave in pulse width
modulator) will shut the converter down.
DATA (Pin 2), CLK (Pin 3)
www.DataSh2e-wet4irUe.scopmrogramming interface.
RST (Pin 4)
PGOOD (Pin 14)
Power Good Indication. PGOOD is an open drain output.
PGOOD will go high impedance when SS voltage greater
than 3.7V and no fault occurs.
This pin be pull low (the Watching Dog = Low), it will
reset some register, when 0x03 bit 0 be setting.
AD_SEL (Pin 5)
RT (Pin 15)
Default operation switching frequency setting. A resistor
is attached to set the default operation frequency.
The pin select series bus address. Pin =1,Address = 0x5E
& Pin = 0, Address = 0x5C.
GND (Pin 6)
CSN (Pin 16)
The pin is defined to sense load current of CPU. The pin
should be connected to the output node of choke.
Chip power ground.
ADJ (Pin 17)
IC_OUT (Pin 7)
The pin is defined as a reference current output. A capacitor
is attached to set the default Watching Dog low pluse
time. Write the index 0x03 bit0 = 1 delay 7 times Tdelay
time then issue Tdelay low pluse,
where Tdelay
= COUT
ICOUT
× VCOUT
FB (Pin 8)
The pin is defined as an inverting input of internal error
amplifier.
Pin for active droop adjustment. An external resistor is
attached to GND for load droop setting.
CSP1 (Pin 21), CSP2 (Pin 20), CSP3 (Pin 19),
CSP4 (Pin 18)
Current sense inputs from the individual converter
channels.
PWM1 (Pin 22), PWM2 (Pin 23), PWM3 (Pin 24),
PWM4 (Pin 25)
PWM outputs for each phase switching drive.
COMP (Pin 9)
The pin is defined as an output of the error amplifier and an
input of the PWM comparator.
VDD (Pin 26)
Chip powers supply. Connect this pin to a 5VSB or VCC5
supply.
SGND (Pin 10)
Difference ground sense of VCORE.
VID4 (Pin 27), VID3 (Pin 28), VID2 (Pin 29),
VID1 (Pin 30), VID0 (Pin 31), VID5 (Pin 32)
VOSS (Pin 11)
VCORE initial value offset. Connect this pin to GND with a
resistor to set the offset value.
DAC voltage identification. The pins are internally pulled
to 1.2V (pull high 50μA) if left open.
GND (Exposed Pad (33)]
DVD (Pin 12)
Hardware adjustable system power UVLO detection; input
The exposed pad must be soldered to a large PCB and
connected to GND for maximum power dissipation.
DS8801B-04 August 2007
All brandname or trademark belong to their owner respectively
www.richtek.com
5
5 Page 
Preliminary
RT8801B
Typical Operating Characteristics
450
400
350
300
250
200
www.DataSheet4U.c1o5m0
100
50
0
0
Adjustable Frequency
20 40 60 80 100 120
RRT (kΩ))
3
2.8
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0
Linearity of each PWM
PWM2
PWM3
PWM1
PWM4
fOSC = 200k
500 1000 1500 2000 2500 3000 3500
Pulse Width (ns)
VCORE
Load Transient Response
VCORE
Load Transient Response
Phase
IOUT
VADJ
CH1: (500mV/Div)
CH2: (10V/Div)
CH3: (50A/Div)
CH4: (100mV/Div)
Time (5μs/Div)
Phase1
Phase2
Phase3
CH1: (500mV/Div), CH2: (10V/Div)
CH3: (10V/Div), CH4: (10V/Div)
Time (5μs/Div)
PWM
Relationship Between Inductor
Current and VADJ
CH1:(5V/Div)
CH2:(5V/Div)
VSS
VADJ
IL CH3:(50mV/Div)
CH4:(20A/Div)
Time (25ms/Div)
PWM
UGATE
LGATE
VCOMP
Power-Off @ IOUT = 60A
CH1:(5V/Div)
CH2:(20V/Div)
CH3:(10V/Div)
CH4:(1V/Div)
Time (10μs/Div)
DS8801B-04 August 2007
All brandname or trademark belong to their owner respectively
www.richtek.com
11
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| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet RT8801B.PDF ] | |
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