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PDF TMP92FD54AIF Data sheet ( Hoja de datos )
| Número de pieza | TMP92FD54AIF | |
| Descripción | CMOS 32-bit Micro-controller | |
| Fabricantes | Toshiba Semiconductor | |
| Logotipo |  |
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CMOS 32-bit Micro-controller
TMP92FD54AIF
TMP92FD54AI
1. Outline and Device Characteristics
TMP92FD54AI is high-speed advanced 32-bit micro-controller developed for controlling
equipment which processes mass data.
TMP92FD54AI is a micro-controller which has a high-performance CPU (900/H1 CPU) and
various built-in I/Os. TMP92FD54AI is housed in a 100-pin mini flat package.
Device characteristics are as follows:
(1)
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(2)
CPU : 32-bit CPU(900/H1 CPU)
Compatible with TLCS-900,900/L,900/L1,900/H,900/H2’s instruction code
16Mbytes of linear address space
General-purpose register and register banks
Micro DMA : 8channels (250ns / 4bytes at fc = 20MHz, best case)
Minimum instruction execution time : 50ns(at 20MHz)
Internal data bus : 32-bit
Internal memory
Internal RAM : 32K-byte
Internal ROM : 512K-byte Flash E2PROM
3K-byte Mask ROM (for Flash boot mode)
92FD54AI-1
2006-01-27
1 page  
2. Pin Assignment and Functions
2.1 Pin Assignment
TMP92FD54AI
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ADVSS
ADVCC
VREFL
VREFH
RX/PF7
TX/PF6
CTS1/SCLK1/PF5
RXD1/PF4
TXD1/PF3
CTS0/SCLK0/PF2
RXD0/PF1
TXD0/PF0
DVSS
PM4/SCK2
DVCC5
A8/SS/PM0
A9/MOSI/PM1
A10/MISO/PM2
A11/SECLK/PM3
D0/P00
D1/P01
D2/P02
D3/P03
D4/P04
D5/P05
01
05
10
15
20
25
TMP92FD54AIF
(P-LQFP100-1414-0.50C)
14 x 14 x 1.4
TOP VIEW
75 DVCC5
X1
DVSS
X2
TEST1
70 XT1
XT2
DVCC3
PN6/SO2/SDA2/A15
PN5/SI1/SCL1/A14
65 PN4/SO1/SDA1/A13
PN3/SCK1/A12
DVSS
PN2/SI0/SCL0
DVCC5
60 PN1/SO0/SDA0
PN0/SCK0
PC0/TI0/INT1
PC1/TO1
PC2/TO3/INT2
55 PC3/TI4/INT3
PC4/TO5
PC5/TO7/INT4
REGEN
51 DVSS
92FD54AI-5
2006-01-27
5 Page 
TMP92FD54AI
JEDEC-based functions
Auto Program
Auto Chip Erase
Auto Block Erase
Data Polling / Toggle Bit
Functions which have been changed, added or removed
<Changed> Block Protect (supports only software protection.)
<Removed> Erase Resume/Suspend function
4.1.2 Block diagram of the flash unit
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Internal Address Bus
Internal Data Bus
Internal Control Bus
Mode set-
up pin
Mode Control
ROM Controller / Interleave Control
Control
Address
Data
Flash memory
RDY/BSY output
Control
Circuit
(including
automatic
sequence
control
circuit)
Command
Register
Address Latch
Data Latch
Column Decoder / Sense Amp
Flash Memory Cell
512 KB
Erase Block Decoder
Figure 4.1.1 Block diagram of the flash unit
92FD54AI-11
2006-01-27
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TMP92FD54AIF.PDF ] | |
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