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PDF TSC695F Data sheet ( Hoja de datos )
| Número de pieza | TSC695F | |
| Descripción | Rad-Hard 32-bit SPARC Embedded Processor | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Integer Unit Based on SPARC V7 High-performance RISC Architecture
• Optimized Integrated 32/64-bit Floating-point Unit
• On-chip Peripherals
– EDAC and Parity Generator and Checker
– Memory Interface
Chip Select Generator
Waitstate Generation
Memory Protection
– DMA Arbiter
– Timers
General Purpose Timer (GPT)
Real-time Clock Timer (RTCT)
Watchdog Timer (WDT)
www.DataSh–eeItn4Ute.crroumpt Controller with 5 External Inputs
– General Purpose Interface (GPI)
– Dual UART
• Speed Optimized Code RAM Interface
8- or 40-bit boot-PROM (Flash) Interface
• IEEE 1149.1 Test Access Port (TAP) for Debugging and Test Purposes
• Fully Static Design
• Performance: 12 MIPs/3 MFlops (Double Precision) at SYSCLK = 15 MHz
• Core Consumption: 1.0W Typ. at 20 MIPs/0.7W typ. at 10 MIPs
• Operating Range: 4.5V to 5.5V(1) -55°C to +125°C
• Total Dose Radiation Capability (Parametric and Functional): 300 KRADs (Si)
• SEU Event Rate Better than 3 E-8 Error/Component/Day (Worst Case)
• Latch-up Immunity Better than (LET) 100 MeV-cm2/mg
• Quality Grades: ESA SCC, QML Q or V
• Package: 256 MQFPF; Bare Die
Note: 1. For 3.3V capability see the TSC695FL datasheet on the Atmel site.
Rad-Hard 32-bit
SPARC
Embedded
Processor
TSC695F
Description
The TSC695F (ERC32 Single-Chip) is a highly integrated, high-performance 32-bit
RISC embedded processor implementing the SPARC architecture V7 specification. It
has been developed with the support of the ESA (European Space Agency), and
offers a full development environment for embedded space applications.
The processor is manufactured using the Atmel 0.5 µm radiation tolerant (≥ 300
KRADs (Si)) CMOS enhanced process (RTP). It has been specially designed for
space, as it has on-chip concurrent transient and permanent error detection.
The TSC695F includes an on-chip Integer Unit (IU), a Floating Point Unit (FPU), a
Memory Controller and a DMA arbiter. For real-time applications, the TSC695F offers
a high security watchdog, two timers, an interrupt controller, parallel and serial inter-
faces. Fault tolerance is supported using parity on internal/external buses and an
EDAC on the external data bus. The design is highly testable with the support of an
On-Chip Debugger (OCD), and a boundary scan through JTAG interface.
Rev. 4118H–AERO–06/03
1 page  
TSC695F
Product Description
Integer Unit
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Floating-point Unit
The Integer Unit (IU) is designed for highly dependable space and military applications,
and includes support for error detection. The RISC architecture makes the creation of a
processor that can execute instructions at a rate approaching one instruction per pro-
cessor clock possible.
To achieve that rate of execution, the IU employs a four-stage instruction pipeline that
permits parallel execution of multiple instructions.
• Fetch - The processor outputs the instruction address to fetch the instruction.
• Decode - The instruction is placed in the instruction register and is decoded. The
processor reads the operands from the register file and computes the next
instruction address.
• Execute - The processor executes the instruction and saves the results in temporary
registers. Pending traps are prioritized and internal traps are taken during this stage.
• Write - If no trap is taken, the processor writes the result to the destination register.
All four stages operate in parallel, working on up to four different instructions at a time. A
basic ‘single-cycle’ instruction enters the pipeline and completes infour cycles.
By the time it reaches the write stage, three more instructions have entered and are
moving through the pipeline behind it. So, after the first four cycles, a single-cycle
instruction exits the pipeline and a single-cycle instruction enters the pipeline on every
cycle. Of course, a ’single-cycle’ instruction actually takes four cycles to complete, but
they are called single cycle because with this type of instruction the processor can com-
plete one instruction per cycle after the initial four-cycle delay.
The FLoating Point Unit (FPU) is designed to provide execution of single and double-
precision floating-point instructions concurrently with execution of integer instructions by
the IU. The FPU is compliant to the ANSI/IEEE-754 (1985) floating-point standard.
The FPU is designed for highly dependable space and military applications, and
includes support for concurrent error detection and testability.
The FPU uses a four stage instruction pipeline consisting of fetch, decode, execute and
write stages (F, D, E and W). The fetch unit captures instructions and their addresses
from the data and address buses. The decode unit contains logic to decode the floating-
point instruction opcodes. The execution unit handles all instruction execution. The exe-
cution unit includes a floating-point queue (FP queue), which contains stored floating-
point operate (FPop) instructions under execution and their addresses. The execution
unit controls the load unit, the store unit, and the datapath unit. The FPU depends upon
the IU to access all addresses and control signals for memory access. Floating-point
loads and stores are executed in conjunction with the IU, which provides addresses and
control signals while the FPU supplies or stores the data. Instruction fetch for integer
and floating-point instructions is provided by the IU.
The FPU provides three types of registers: f registers, FSR, and the FP queue. The FSR
is a 32-bit status and control register. It keeps track of rounding modes, floating-point
trap types, queue status, condition codes, and various IEEE exception information. The
floating-point queue contains the floating-point instruction currently under execution,
along with its corresponding address.
4118H–AERO–06/03
5
5 Page 
TSC695F
Timers
General Purpose Timer
Real Time Clock Timer
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Watchdog Timer
UARTs
General Purpose Interface
Execution Modes
Reset Mode
In software debug mode the timers are controlled by a system register bit and the exter-
nal pin DEBUG.
The General Purpose Timer (GPT) provides, in addition to a generalized counter func-
tion, a mechanism for setting the step size in which actual time counts are performed.
GPT is clocked by the internal system clock. They are possible to program to be either
of single-shot type or periodical type and in both cases generate an interrupt when the
delay time has elapsed. The current value of the scaler and counter of the GPT can be
read.
The only functional differences between the two timers are that the Real Time Clock
Timer (RTCT) has an 8-bit scaler (16-bit scaler for GPT) and that the RTCT interrupt has
higher priority than the GPT interrupt.
RTCT information is available on RTC output pin.
Setting the external pin IWDE to VCC enables the internal watchdog timer. Otherwise the
watchdog function must be externally provided.
The watchdog is supplied from a separate external input (WDCLK). After reset, the timer
is enabled and starts running with the maximum range. If the timer is not refreshed
(reprogrammed) before the counter reaches zero value, an interrupt is sent. Simulta-
neously, the timer starts counting a reset time-out period. If the timer is not
acknowledged before the reset time-out period elapses, a reset is applied to TSC695F.
Two full duplex asynchronous receiver transmitters (UART) are included. In software
debug mode the UART’s are controlled by system register bits.
The data format of the UART’s is eight bits. It is possible to choose between even or odd
parity, or no parity, and between one and two stop bits. The UART’s provide double buff-
ering, i.e. each UART consists of a transmitter holding register, a receiver holding
register, a transmitter shift register, and a receiver shift register. Each of these registers
are 8-bit wide. For each UART a RX and TX Register is provided. The UART’s generate
an interrupt each time a byte has been received or a byte has been sent. There is
another interrupt to indicate errors.
The baud rate of both the UART’s is programmable. The clock is derived either from the
system clock or can use the watchdog clock.
The General Purpose Interface (GPI) is an 8-bit parallel I/O port. Each pin can be config-
ured as an input or an output.
A falling or rising edge detection is made on each selected GPI inputs. Every input tran-
sition on GPI generates an external positive pulse on GPIINT pin of two SYSCLK width.
Reset mode is entered when:
– The SYSRES input is asserted
– Software reset which is caused by the software writing to a Software Reset
Register
– Watchdog reset which is caused by a Watchdog counter time-out
– Error reset which is caused by a hardware parity error
4118H–AERO–06/03
11
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