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PDF CY8C42423 Data sheet ( Hoja de datos )
| Número de pieza | CY8C42423 | |
| Descripción | (CY8C42xx3) Power Devices | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de CY8C42423 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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PRELIMINARY
CY8C42123/CY8C42223
CY8C42323/CY8C42423
Power PSoC™ Devices
1.0 Features
1.1 Key Features
• Extended Operating Voltage of 2.5V to 36V
• 2 HV Linear Opamp Control Loops for Driving Power PFETs
• 2 HV Switching Control Loops for Driving External PFETs
• 2 High Voltage CMOS or Open Drain Outputs
www.DataSheet•4U2.cHoimgh Voltage Analog Sense Inputs
• 4KB of Flash
• 256 Bytes of SRAM
1.2 Improved Features
• Very Low Current Mode for 100 nA Sleep (Deep Sleep)
• Analog Absolute Accuracy (0.75%)
• Additional Flexibility for Sleep Modes
• 2 Comparators with DAC References
• 6- to 12-Bit ADC (20 Ksps at 8 Bits)
• Configurable Analog Mux, 10:1 or 5:2 Differential
• Configurable Digital Blocks
— 8- to 16-Bit Timers, Counters, and PWMs
— Connectable to All GPIO Pins
— Connectable to All High Voltage Output Pins
— Single Block Deadband PWM with Kill
— Digital Blocks can Drive Outputs to 36V
— Complex Peripherals by Combining Blocks
1.3 Applications
• Battery Chargers (Linear, Switched, or Fly Back)
• DC-DC Buck and Boost Converters
• Fan Controllers (Tachometer, Temp. Sense, Current Limit)
• Motor Drivers (H-Bridge, Hall-Effect Sensors)
• White LED Drivers
• Temperature Sensor (Thermistor, Thermocouple)
• General-Purpose High Voltage Microcontroller
2.0 Block Diagram
HVdd
GDO1
VS1
HVO[1]
P0[7]
P0[5]
P0[3]
P0[1]
P1[1]
PSoC CORE
SleepandWatchdog
POR andLVD
PSMo8CCCPOURE
4KBFlash
256BSRAM
SystemResets
InterruptController
LowDrop-Out
Regulator
DBC01
InternalVdd
ANALOG and HIGH VOLTAGE
SECTIONS
ODAC1
ODAC0
VDAC1
VBG
VDAC1 IBIAS VDAC0
VDAC0
DBC00
HVDriver
Analogto
Digital
Convertor
HVDriver
IDAC1
Atten1
AMuxBus3
AMuxBus1
COMP1
ODAC1
Atten0
AMuxBus2
AMuxBus0
IDAC0
ODAC0
COMP0
Gl o bal Di gi tal In terco nnectBus
System Bus
DBC00 DBC01
DBD02
DigitalPSoC BlockArray
DIGITAL SYSTEM
DBD03
1DigitalRow
GDO0
VS0
HVO[0]
P0[6]
P0[4]
P0[2]
P0[0]
P1[0]
SYSTEMRESOURCES
LowSpeed
Oscillator
Internal
Voltag e
Reference
Internal
Main
Oscillator
I2C
Digital
Clocks
Cypress Semiconductor Corporation
Document 38-12034 Rev. *C
Figure 2-1. Block Diagram
• 198 Champion Court •
San Jose, CA 95134 • 408.943.2600
Revised November 17, 2005
1 page  
PRELIMINARY
CY8C42123/CY8C42223
CY8C42323/CY8C42423
5.0 Typical Power PSoC Applications
5.1 Boost Converter White LED Driver
A white LED driver is a constant current power supply. By driving the same current through a set of LEDs in series, the intensity
of the LEDs can be closely matched. The CY8C42x23 Power PSoC can be configured as a constant voltage or constant current
boost supply. In this configuration, the HVdd voltage is lower than required to drive the LEDs in series and a higher voltage must
be generated. White LEDs typically have a forward voltage of around 4V, so in the five LED configuration shown in Figure 5-1
the LED drive voltage would have to be around 20V (plus allowance for the voltage losses in the FET and the current sense
resistor, RISENSE).
Figure 5-1 shows an inductor, an NFET, a diode, and a capacitor configured as a boost converter with the CY8C42x23 as the
controller. The voltage on the capacitor is fed back through a voltage sense pin, VS0, and an attenuator, Atten0, to the comparator,
www.DataSheeTCt4hOUeM.coPoum0tp. uTthoef
VS0 pin can be
the comparator
connected directly to a
controls a single PSoC
voltage higher than HVdd, so
digital block configured as a
no external signal level conversion is needed.
PWM. The reference for the comparator is the
output of VDAC0. When the attenuator output exceeds the reference, the comparator will stop the PWM using the "Kill" input.
This creates a feedback loop that maintains the VS0 node at a voltage proportional to the VDAC0 setting. The Atten0 output is
also connected to the ADC so the control software can monitor the output voltage.
To maintain constant current, the voltage across the RISENSE resistor is routed through pin P0[4] and AMuxBus0 to the ADC
where it is monitored. The control software adjusts the VDAC0 setting, based on current sense measurements, to achieve the
desired current through the load.
5.1.1 Resources
This application could connect the RISENSE resistor to any of the GPIO pins (P0[7:0] and P1[1:0]). The Power PSoC still has three
digital blocks, half of the high voltage resources, one VDAC, two IDACs, seven of the analog multiplexer channels to the ADC,
and over 90% of the CPU available for other tasks.
HVdd
HVdd
HVdd
GDO1
VS1
H VO[1]
P0[7]
P0[5]
P0[3]
P0[1]
P1[1]
Low Drop-Out
Reg ulator
D BC 01
Internal Vdd
ANALOG and HIGH V OLTAGE
SECTIONS
OD AC 1
VDAC1
VDAC1
VBG
IBIAS
ODAC0
VD AC 0
VDAC0
D BC 00
HV Driver
Analog to
Dig ital
Convertor
HV Driver
ID AC 1
COMP 1
Atten1
AM uxBus3
AM uxBus1
ODAC1
Atten0
AM uxBus2
AM uxBus0
IDAC0
OD AC 0
COMP 0
GD O0
VS0
HVO[0]
P0[6]
P0[4]
P0[2]
P0[0]
P1[0]
Q1
RISENSE
Kill PWM primary
PWM DB
DCB00
DCB01
DBD02
DIGITAL SECTION
DCD03
Figure 5-1. Boost Converter White LED Driver
Document 38-12034 Rev. *C
Page 5 of 42
5 Page 
PRELIMINARY
CY8C42123/CY8C42223
CY8C42323/CY8C42423
6.1.4 32-Pin QFN Part Pinouts
The 32-pin QFN part is for the CY8C42423 PSoC device.
32-Pin Part Pinout (QFN**)
Pin
No.
1
2 HVO
3
4
www.DataSheet45U.com IO
I
6 IO
I
7 IO
I
8 IO
I
9
10
11 IO
I
12 Power
13 IO
I
14
15
16
17 IO
I
18 IO
I
19 IO
I
20 IO
I
21 I
22
23
24 HVO
25
26 HVI
27 HVO HVO
28 Power
29 Power
30 HVO HVO
31 HVI
32
CP Power
Name
Description
NC No Connection
HVO[1] High Voltage Output 1
NC No Connection
NC No Connection
P0[7] I2C Clock
P0[5] I2C Data
P0[3]
P0[1]
NC No Connection
NC No Connection
P1[1] I2C Clock*
Vss
P1[0] I2C Data*
NC No Connection
NC No Connection
NC No Connection
P0[0]
P0[2] Optional External CLK Input (EXTCLK)
P0[4]
P0[6] Optional External Voltage Reference
(EXTREF)
XRES External Reset
NC No Connection
NC No Connection
HVO[0] High Voltage Output 0
DNU Do Not Use
VS0 High Voltage Sense 0
GD0 High Side Gate Driver 0
HVdd
HVdd
GD1
Supply Voltage
Supply Voltage
High Side Gate Driver 1
VS1 High Voltage Sense 1
NC No Connection
Vss Center Pad Must be Connected to Ground
CY8C42423 PSoC Device
NC
HV O[1]
NC
NC
P0[7]
P0[5]
P0[3]
P0[1]
1
2
3
4
5
6
7
8
QFN
(Top View )
(CP)
24 HV O[0]
23 NC
22 NC
21 XRES
20 P0[6]
19 P0[4]
18 P0[2]
17 P0[0]
LEGEND I = Input 5V Only, O = Output 5V Only, HV = High Voltage, NC = No Connection.
* These are the ISSP pins, which are not HighZ at POR (Power On Reset). See the Power PSoC Mixed-Signal Array Technical Reference Manual for details.
**The QFN package has a center pad (CP) that must be connected to ground (Vss).
Important Note For information on the preferred dimensions for mounting QFN packages, see the following Application Note at
http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.
Document 38-12034 Rev. *C
Page 11 of 42
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CY8C42423.PDF ] | |
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