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PDF AKD4121 Data sheet ( Hoja de datos )
| Número de pieza | AKD4121 | |
| Descripción | Evalation Board | |
| Fabricantes | Asahi Kasei Microsystems | |
| Logotipo |  |
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ASAHI KASEI
[AKD4121]
AKD4121
AK4121 Evalation Board Rev.B
GENERAL DESCRIPTION
The AKD4121 is the evaluation board for the AK4121, 96kHz asynchronous sample rate converter. This
board has the optical connectors to interface with other digital audio equipments and serial interfaces for
AKM AD/DA evaluation boards. The AKD4121 achieves quick evaluation of AK4121
Ordering guide
www.DataSheet4U.com
AKD4121 --- Evaluation board for AK4121
FUNCTION
Optical fiber connectors (for Digital Audio Interface. input x 1, output x 1.)
10pin Header (for AKM AD/DA evaluation board. input x 1, output x 1.)
On board X’tal Oscillator (input x 1, output x 1.)
5V or 3.3V
JP1
IMCLK
+3.3V
JACK
REG
JP10
3.3V
T1
48M003F
OUT
IN
PORT1
OUT
IMCLK
IN
IBICK
ILRCK
SDTI
10pin Header
3
+3.3V D5V
+3.3V
D5V
PORT2
Optical
Input
DIR
(AK4112B)
3 JP2 ~4 3
2
AK4121
3
3
2
D5V
JP11
Bypass
JP6
DIT-SOURCE
DIR
PORT3
JP5
SRC-MCLK
PORT3
DIT
3
+3.3V D5V
PORT3
Clock
Generator
OMCLK
OBICK
OLRCK
SDTO
10pin Header
PORT4
3 3 DIT
JP7~9
(AK4114)
Optical
Output
SW1 SW2
PDN SMUTE
SW3
fsi-DIR
SW4
CMODE
SW5
fso
Figure 1. AKD4121 Block Diagram
*Circuit diagram and PCB layout are attached at the end of this manual.
<KM069301>
-1-
2004/08
1 page  
ASAHI KASEI
1-2. All clock are fed through the 10-pin port
1-2-a. Jumper setting
www.DataSheet4U.com
Parts No.
Setting
JP1 (don’t care)
JP2 OPEN
JP3 OPEN
JP4 OPEN
SW3-4
(don’t care)
X1 (don’t care)
Table 2. Jumper Setting (Refer following figures)
JP1 JP2 JP3 JP4
OUT
IN
IMCLK
IBICK
SDTI
ILRCK
Figure 4. Jumper Setting
1-2-b. Audio Interface Format setting
Audio Interface
Format
SW3-1
DIF2
SRC:AK4121
SW3-2
DIF1
SW3-3
DIF0
16bit, Right justified
0
0
0
20bit, Right justified
0
0
1
Left justified
0
1
0
I2S 0 1 1
24bit, Right justified
1
0
0
Table 3. DIP switch (SW3) setting(Refer following figures)
[AKD4121]
12345
fsi-DIR 1/2MCLK
SW3
16bit, Right justified
12345
fsi-DIR 1/2MCLK
SW3
20bit, Right justified
<KM069301>
-5-
2004/08
5 Page 
ASAHI KASEI
[AKD4121]
2-2. Clocks are fed through the 10-pin port(PORT3)
2-2-1. AK4121 in Master Mode
2-2-1-a. Jumper setting
www.DataSheet4U.com
Parts No.
Setting
JP5 PORT3
JP6 OPEN
JP8 OPEN
JP9 OPEN
JP7 OPEN
JP11 OPEN
Table 8. Jumper setting(Refer following figures)
JP5
DIT
JP6 JP8 JP9 JP7
PORT3
JP11
PORT3
DIR
SRC-MCLK DIT-SOURCE
OBICK OLRCK
Using X’tal on-board
Figure 10. Jumper setting
SDTO
10pin
Bypass
Output
2-2-1-b. Audio Interface Format
Mod SW4-1 SW4-2 SW4-3
e CMODE2 CMODE1 CMODE0
MCLK
Master/Slave (Output Port)
0 L L L 256fso (fso~96kHz)
Master
1 L L H 384fso (fso~96kHz)
Master
2 L H L 512fso (fso~48kHz)
Master
3 L H H 768fso (fso~48kHz)
Master
Table 9. AK4121 System Clock setting
<KM069301>
- 11 -
2004/08
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AKD4121.PDF ] | |
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