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PDF CY7C151xV18 Data sheet ( Hoja de datos )
| Número de pieza | CY7C151xV18 | |
| Descripción | (CY7C1xxxxVxx) RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata | |
| Fabricantes | Cypress Semiconductor | |
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CY7C129*DV18/CY7C130*DV25
CY7C130*BV18/CY7C130*BV25/CY7C132*BV25
CY7C131*BV18 / CY7C132*BV18/CY7C139*BV18
CY7C191*BV18/CY7C141*AV18 / CY7C142*AV18/
CY7C151*V18 /CY7C152*V18
May 02, 2007
RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata
Errata Revision: *C
This document describes the DOFF issue for QDRII/DDRII and the Output Buffer and JTAG issues for
QDRI/DDRI/QDRII/DDRII. Details include trigger conditions, possible workarounds and silicon revision applicability.
This document should be used to compare to the respective datasheet for the devices to fully describe the device
functionality.
www.DataSheePt4lUe.acsoem contact your local Cypress Sales Representative for availability of the fixed devices and any other questions.
Devices Affected
Density & Revision
9Mb - Ram9(90 nm)
9Mb - Ram9(90 nm)
18Mb - Ram9(90nm)
18Mb - Ram9(90nm)
36Mb - Ram9(90nm)
72Mb -Ram9(90nm)
Part Numbers
CY7C130*DV25
CY7C129*DV18
CY7C130*BV18
CY7C130*BV25
CY7C132*BV25
CY7C131*BV18
CY7C132*BV18
CY7C139*BV18
CY7C191*BV18
CY7C141*AV18
CY7C142*AV18
CY7C151*V18
CY7C152*V18
Architecture
QDRI/DDRI
QDRII
QDRI/DDRI
QDRII/DDRII
QDRII/DDRII
QDRII/DDRII
Table 1. List of Affected devices
Product Status
All of the above densities and revisions are available in sample as well as production quantities.
QDR/DDR DOFF Pin, Output Buffer and JTAG Issues Errata Summary
The following table defines the issues and the fix status for the different devices which are affected.
Item
1.
Issue
DOFF pin is used for enabling/dis-
abling the DLL circuitry within the
SRAM. To enable the DLL circuitry,
DOFF pin must be externally tied
HIGH. The QDR-II/DDR-II devices
have an internal pull down resistor of
~5K Ω . The value of the external pull-
up resistor should be 500 Ω or less in
order to ensure DLL is enabled.
Device
9Mb - “D” Rev - Ram9
18Mb - “B” Rev - Ram9
36Mb - “A” Rev - Ram9
72Mb - Ram9
QDR-II/DDR-II Devices
Fix Status
The fix involved removing the in-
ternal pull-down resistor on the
DOFF pin. The fix has been im-
plemented on the new revision
and is now available.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 001-06217 Rev. *C
Revised:- May 02, 2007
1 page  
In systems where multiple SRAMs with multiple RPS# lines are used, a dummy read operation will have to be
performed on every SRAM on the board. Below is an example sequence of events that can be performed
before valid access can be performed on the SRAM.
1) Initialize the Memory Controller
2) Assert RPS# Low for each of the memory devices
Note:
For all devices with x9 bus configuration, the following sequence needs to be performed:
1) For the 72M / 36M / 18M x9 devices drive address pin A2 / A10 / A3 low respectively and perform dummy
read.
2) For the 72M / 36M / 18M x9 devices drive address pin A2 / A10 / A3 high respectively and perform dummy
read.
www.DataSheet4U.com
If the customer has the trigger conditions met during normal access to the memory then there is no workaround
at this point.
K
/K
/RPS
Address A
DataOut (Q)
WE#
Address A
DataOut (Q)
QDRII Operation
CE
G
Q(A)
Q(A+1) Q(C)
Q(C+1)
Q(E) Q(E+1)
Dummy Read
DDRII Operation
CE
G
DQ(A)
DQ
(A+1)
DQ(C)
DQ
(C+1)
DQ(E)
DQ
(E+1)
Figure 4. Dummy Read Implementation
• FIX STATUS
The fix has been implemented on the new revision and is now available. The new revision is an increment of
the existing revision. Please refer to Table 4 for the list of devices affected, current revision and the new
revision after the fix.
3. JTAG Mode Issue
• ISSUE DEFINITION
If the input clock (K Clock) is left floating when the device is in JTAG mode, spurious high frequency noise on
this input can be interpreted by the device as valid clocks. This could cause the impedance matching circuitry
(ZQ) on the QDR/DDR devices to periodically load itself with incorrect values. These incorrect values in the
ZQ register could force the outputs into a High-Impedance state. The ZQ circuitry requires at least 1000 valid
K clock cycles to drive the outputs from high impedance to low impedance levels.
• PARAMETERS AFFECTED
Document #: 001-06217 Rev. *C
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| PDF Descargar | [ Datasheet CY7C151xV18.PDF ] | |
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