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PDF SG5842JA Data sheet ( Hoja de datos )

Número de pieza SG5842JA
Descripción Highly Integrated Green-Mode PWM Controller
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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No Preview Available ! SG5842JA Hoja de datos, Descripción, Manual

December 2009
SG5842A/SG5842JA — Highly Integrated Green-Mode
PWM Controller
Features
ƒ Green-Mode PWM Controller
ƒ Low Startup Current: 14µA
ƒ Low Operating Current: 4mA
ƒ Programmable PWM Frequency with Hopping
(SG5842JA)
ƒ Peak-Current-Mode Control
ƒ Cycle-by-Cycle Current Limiting
ƒ Synchronized Slope Compensation
ƒ Leading-Edge Blanking (LEB)
ƒ Constant Output Power Limit
ƒ Totem-Pole Output with Soft Driving
ƒ VDD Over-Voltage Protection (OVP)
ƒ Programmable Over-Temperature Protection (OTP)
ƒ Internal Latch Circuit (OTP, OVP)
ƒ Internal Open-Loop Protection
ƒ VDD Under-Voltage Lockout (UVLO)
ƒ GATE Output Maximum Voltage Clamp: 18V
Applications
General-purpose switch-mode power supplies and
flyback power converters, including:
ƒ Notebook Power Adapters
ƒ Open-Frame SMPS
Description
The highly integrated SG5842A/JA series of PWM
controllers provides several features to enhance the
performance of flyback converters. To minimize standby
power consumption, a proprietary green-mode function
provides off-time modulation to continuously decrease
the switching frequency at light-load conditions. To
avoid acoustic-noise problems, the minimum PWM
frequency set above 22KHz. This green-mode function
enables the power supply to meet international power
conservation requirements. To further reduce power
consumption, SG5842A/JA is manufactured using the
BiCMOS process. This allows a low startup current,
around 14µA, and an operating current of only 4mA. As
a result, a large startup resistance can be used.
The SG5842A/JA built-in synchronized slope
compensation achieves stable peak-current-mode
control. SG5842JA integrates a frequency-hopping
function that helps reduce EMI emission of a power
supply with minimum line filters.
SG5842A/JA provides many protection functions. In
addition to cycle-by-cycle current limiting, the internal
open-loop protection circuit ensures safety should an
open-loop or output short-circuit failure occur. PWM
output is disabled until VDD drops below the UVLO lower
limit, then the controller starts again. As long as VDD
exceeds about 24V, the internal OVP circuit is triggered.
An external NTC thermistor can be applied for over-
temperature protection.
SG5842A/JA is available in an 8-pin DIP or SOP
package.
© 2007 Fairchild Semiconductor Corporation
SG5842A/SG5842JA • Rev. 1.4.3
www.fairchildsemi.com

1 page




SG5842JA pdf
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Symbol
VVDD
VVIN
VFB
VSENSE
VRT
VRI
PD
Parameter
Supply Voltage(1)
Input Terminal
Input Voltage to FB Pin
Input Voltage to SENSE Pin
Input Voltage to RT Pin
Input Voltage to RI Pin
Power Dissipation (TA < 50°C )
ΘJA
TJ
TSTG
TL
ESD
Thermal Resistance (Junction-to-Air)
Operating Junction Temperature
Storage Temperature Range
Lead Temperature (Wave Soldering or Infrared, 10 Seconds)
Electrostatic Discharge Capability
Human Body Model,
JESD22-A114
Charged Device
Model, JESD22-C101
Min.
-0.3
-0.3
-0.3
-0.3
-40
-55
Max.
30
30
7.0
7.0
7.0
7.0
DIP 800
SOP 400
DIP 82.5
SOP 141
+125
+150
+260
3
1
Unit
V
V
V
V
V
V
mW
°C/W
°C
°C
°C
KV
Notes:
1. All voltage values, except differential voltage, are given with respect to GND pin.
2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
TA Operating Ambient Temperature
Min.
-20
Max.
+85
Unit
°C
© 2007 Fairchild Semiconductor Corporation
SG5842A/SG582JA • Rev. 1.4.3
5
www.fairchildsemi.com

5 Page





SG5842JA arduino
Functional Description (Continued)
Limited Power Control
The FB voltage increases every time the output of the
power supply is shorted or overloaded. If the FB voltage
remains higher than a built-in threshold longer than tD-
OLP, PWM output is turned off. As PWM output is turned
off, the supply voltage VDD begins decreasing.
tD-OLP (ms) = 2.154 × RI(K Ω )
(2)
When VDD goes below the turn-off threshold (eg.
10.5V), the controller is totally shut down. VDD is
charged up to the turn-on threshold voltage of 16.5V
through the startup resistor until PWM output is
restarted. This protection feature remains activated as
long as the overloading condition persists. This
prevents the power supply from overheating due to
overloading conditions.
Protection Latch Circuit
The built-in latch function provides a versatile protection
feature that does not require external components (see
ordering information for a detailed description). To reset
the latch circuit, disconnect the AC line voltage of the
power supply.
Thermal Protection
An external NTC thermistor can be connected from the
RT pin to ground. A fixed current, IRT, is sourced from
the RT pin. Because the impedance of the NTC
decreases at high temperatures, when the voltage of
the RT pin drops below 1.05V, PWM output is latched
off. The RT pin output current is related to the PWM
frequency programming resistor RI.
Noise Immunity
Noise from the current sense or the control signal may
cause significant pulse width jitter, particularly in
continuous-conduction mode. Slope compensation
helps alleviate this problem. Good placement and
layout practices should be followed. Avoid long PCB
traces and component leads. Compensation and filter
components should be located near the SG5842A/JA.
Increasing the power-MOS gate resistance is advised.
© 2007 Fairchild Semiconductor Corporation
SG5842A/SG582JA • Rev. 1.4.3
11
www.fairchildsemi.com

11 Page







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