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PDF CY29351 Data sheet ( Hoja de datos )
| Número de pieza | CY29351 | |
| Descripción | 9-Output Zero Delay | |
| Fabricantes | Cypress Semiconductor | |
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PRELIMINARY
CY29351
2.5V or 3.3V, 200 MHz,
9-Output Zero Delay
Features
■ Output frequency range: 25 MHz to 200 MHz
■ Input frequency range: 25 MHz to 200 MHz
■ 2.5V or 3.3V operation
■ Split 2.5V/3.3V outputs
www.DataSh■ee±t24.U5.%commax Output duty cycle variation
■ 9 clock outputs: Drive up to 18 clock lines
■ Two reference clock inputs: LVPECL or LVCMOS
■ 150-ps max output-output skew
■ Phase-locked loop (PLL) bypass mode
■ Spread Aware™
■ Output enable/disable
■ Pin-compatible with MPC9351
■ Industrial temperature range: –40°C to +85°C
■ 32-pin 1.0-mm TQFP package
Functional Description
The CY29351 is a low voltage high performance 200 MHz
PLL-based zero delay buffer designed for high speed clock distri-
bution applications.
The CY29351 features LVPECL and LVCMOS reference clock
inputs and provides 9 outputs partitioned in four banks of one,
one, two, and five outputs. Bank A divides the VCO output by two
or four while the other banks divide by four or eight per SEL(A:D)
settings (Table 3, “Function Table,” on page 3). These dividers
allow output to input ratios of 4:1, 2:1, 1:1, 1:2, and 1:4. Each
LVCMOS compatible output can drive 50Ω series or parallel
terminated transmission lines. For series terminated trans-
mission lines, each output can drive one or two traces giving the
device an effective fanout of 1:18.
The PLL is ensured stable given that the VCO is configured to
run between 200 MHz to 500 MHz. This allows a wide range of
output frequencies from 25 MHz to 200 MHz. For normal
operation, the external feedback input, FB_IN, is connected to
one of the outputs. The internal VCO is running at multiples of
the input reference clock set by the feedback divider (Table 2,
“Frequency Table,” on page 3).
When PLL_EN# is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully static
and the minimum input clock frequency specification does not
apply.
Block Diagram
SELA
PLL_EN
REF_SEL
TCLK
PECL_CLK
Phase
Detector
VCO
200 -
500 MHz
LPF
÷2 / ÷4
÷4 / ÷8
QA
QB
FB_IN
SELB
SELC
OE#
SELD
÷4 / ÷8
÷4 / ÷8
QC0
QC1
QD0
QD1
QD2
QD3
QD4
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-07475 Rev. *B
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 21, 2008
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PRELIMINARY
CY29351
AC Electrical Specifications
(VDD = 2.5V ± 5%, TA = –40°C to +85°C)[7]
Parameter
Description
Condition
fVCO
fin
VCO frequency
Input frequency
÷2 feedback
÷4 feedback
÷8 feedback
Bypass mode (PLL_EN = 0)
www.DataShefreetfD4UC.com
VPP
VCMR
tr , tf
fMAX
Input duty cycle
Peak-Peak input voltage
Common mode range[8]
TCLK input rise/fall time
Maximum output frequency
LVPECL
LVPECL
0.7V to 1.7V
÷2 output
÷4 output
÷8 output
DC Output duty cycle
fMAX < 100 MHz
fMAX > 100 MHz
tr , tf Output rise/fall times
0.6V to 1.8V
t(φ) Propagation delay (static phase offset) TCLK to FB_IN
PCLK to FB_IN
tsk(O)
tPLZ, HZ
tPZL, ZH
BW
Output-to-Output skew
Output disable time
Output enable time
PLL closed loop bandwidth (–3dB)
÷2 feedback
÷4 feedback
÷8 feedback
tJIT(CC)
Cycle-to-Cycle jitter
Same frequency
Multiple frequencies
tJIT(PER)
Period jitter
Same frequency
Multiple frequencies
tJIT(φ)
tLOCK
IO phase jitter
Maximum PLL lock time
Min
200
100
50
25
0
25
500
1.2
–
100
50
25
47.5
45
0.1
–100
–100
–
–
–
–
–
–
–
–
–
–
–
–
Typ.
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
2.2
0.85
0.6
–
–
–
–
175
–
Max
380
190
95
47.5
200
75
1000
VDD – 0.6
1.0
190
95
47.5
52.5
55
1.0
100
100
150
10
10
–
–
–
150
250
100
175
–
1
Unit
MHz
MHz
%
mV
V
ns
MHz
%
ns
ps
ps
ns
ns
MHz
ps
ps
ps
ms
Notes
7. AC characteristics apply for parallel output termination of 50Ω to VTT. Parameters are guaranteed by characterization and are not 100% tested.
8. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies
within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(φ).
Document Number: 38-07475 Rev. *B
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| PDF Descargar | [ Datasheet CY29351.PDF ] | |
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