PDF PPC440EP Data sheet ( Hoja de datos )

Número de pieza	PPC440EP
Descripción	Power PC 440EP Embedded Processor
Fabricantes	AMCC
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No Preview Available ! Part Number 440EP Revision 1.26 – April 25, 2007 440EP Power PC 440EP Embedded Processor Data Sheet Features • PowerPC® 440 processor core operating up to 667MHz with 32KB I-cache and D-cache with parity checking. • Selectable processor:bus clock ratios of N:1, N:2. www.DataSheet4•U.cFolmoating Point Unit with single- and double- precision and single-cycle throughput. • Dual bridged Processor Local Buses (PLBs) with 64- and 128-bit widths. • Double Data Rate (DDR) Synchronous DRAM (SDRAM) interface operating up to 133MHz with ECC. • DMA support for external peripherals, internal UART and memory. • PCI V2.2 interface (3.3V only). Thirty-two bits at up to 66MHz. • Programmable interrupt controller supports interrupts from a variety of sources. • Programmable General Purpose Timers (GPT). • Two Ethernet 10/100Mbps half- or full-duplex interfaces. Operational modes supported are MII, RMII, and SMII with packet reject. • Up to four serial ports (16750 compatible UART). • Two USB ports. One USB 1.1 Host interface with on-chip PHY. One USB 2.0 Device interface, with dedicated DMA, configured as a 1.1 on-chip PHY or a 2.0 UTMI. • External peripheral bus (16-bit data) for up to six devices with external mastering. • Two IIC interfaces (one with boot parameter read capability). • NAND Flash interface. • SPI interface. • General Purpose I/O (GPIO) interface. • JTAG interface for board level testing. • Boot from PCI memory, NOR Flash on the external peripheral bus, or NAND Flash on the NAND Flash interface. • Available in RoHS compliant lead-free package. Description Designed specifically to address high-end embedded applications, the PowerPC 440EP (PPC440EP) provides a high-performance, low- power solution that interfaces to a wide range of peripherals and incorporates on-chip power management features. This chip contains a high-performance RISC processor, a floating point unit, DDR SDRAM controller, PCI bus interface, control for external ROM and peripherals, DMA with scatter-gather support, Ethernet ports, serial ports, IIC interfaces, SPI interface, USB ports, NAND Flash interface, and general purpose I/O. Technology: CMOS Cu-11, 0.13μm. Package: 35mm, 456-ball standard plastic ball grid array (E-PBGA), with and without lead (RoHS compliant). Typical power (measured): Less than 3W at 533MHz, 2.5W at 400MHz. Supply voltages required: 3.3V, 2.5V, 1.5V. AMCC Proprietary 1 1 page 440EP – PPC440EP Embedded Processor Block Diagram Revision 1.26 – April 25, 2007 Data Sheet Figure 2. PPC440EP Functional Block Diagram 10 External Interrupts Clock Control Reset Power Mgmt UIC www.DataSheet4U.com FPU Timers MMU PPC440 Processor Core JTAG 32 KB D-Cache Trace 32 KB I-Cache Performance Monitor PLB (PLB4—128 bits) DCRs DCR Bus PLB Bridge 66MHz max - 30-bit addr - 16-bit data 66MHz max - 32 bits - 6 devices External NAND Peripheral Flash Controller Controller PCI Bridge PLB (PLB3—64 bits) DMA OPB Controller Bridge OPB Bridge DMA Controller GPT DDR SDRAM Controller OPB 1 On-chip Peripheral Bus (OPB 0) 266MHz max - 13-bit addr - 32-bit data USB 2.0 Device UTMI 1.1PHY USB 1.1 Host 1.1PHY GPIO SPI D+/D− D+/D− IIC x2 BSC UART Ethernet x4 10/100 x2 MAL ZMII 1 MII or 2 RMII or 2 SMII The PPC440EP is a system on a chip (SOC) using IBM CoreConnect Bus™ Architecture. AMCC Proprietary 5 5 Page 440EP – PPC440EP Embedded Processor Revision 1.26 – April 25, 2007 Data Sheet PCI Interface The PCI interface allows connection of PCI devices to the PowerPC processor and local memory. This interface is designed to Version 2.2 of the PCI Specification and supports 32- bit PCI devices. Reference Specifications: • PowerPC CoreConnect Bus (PLB) Specification Version 3.1 • PCI Specification Version 2.2 • PCI Bus Power Management Interface Specification Version 1.1 Features include: • PCI 2.2 www.DataSheet4U.co–m Frequency to 66MHz – 32-bit bus • PCI Host Bus Bridge or an Adapter Device's PCI interface • Internal PCI arbitration function, supporting up to six external devices, that can be disabled for use with an external arbiter • Support for Message Signaled Interrupts • Simple message passing capability • Asynchronous to the PLB • PCI Power Management 1.1 • PCI register set addressable both from on-chip processor and PCI device sides • Ability to boot from PCI bus memory • Error tracking/status • Supports initiation of transfer to the following address spaces: – Single beat I/O reads and writes – Single beat and burst memory reads and writes – Single beat configuration reads and writes (type 0 and type 1) – Single beat special cycles DDR SDRAM Memory Controller The Double Data Rate (DDR) SDRAM memory controller supports industry standard discrete devices. Up to four 256MB logical banks are supported in limited configurations. Global memory timings, address and bank sizes, and memory addressing modes are programmable. Features include: • Registered and non-registered industry standard discrete devices • 32-bit memory interface with optional 8-bit ECC (SEC/DED) • Sustainable 1.1GB/s peak bandwidth at 133MHz • SSTL_2 logic • 1 to 4 chip selects • CAS latencies of 2, 2.5 and 3 supported • DDR200/266 support • Page mode accesses (up to eight open pages) with configurable paging policy • Programmable address mapping and timing • Hardware and software initiated self-refresh • Power management (self-refresh, suspend, sleep) AMCC Proprietary 11 11 Page

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