PDF ICS84021 Data sheet ( Hoja de datos )

Número de pieza	ICS84021
Descripción	CRYSTAL-TO LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Fabricantes	Integrated Circuit Systems
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No Preview Available ! Integrated Circuit Systems, Inc. ICS84021 260MHZ, CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER GENERAL DESCRIPTION ICS The ICS84021 is a general purpose, Crystal-to- LVCMOS/LVTTL High Frequency Synthesizer HiPerClockS™ and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS84021 has a selectable TEST_CLK or crys- tal input. The VCO operates at a frequency range of 620MHz to 780MHz. The VCO frequency is programmed in steps equal to the value of the input reference or crystal frequency. www.DataSheeTt4hUe.cVomCO and output frequency can be programmed using the serial or parallel interface to the configuration logic. The low phase noise characteristics of the ICS84021 make it an ideal clock source for Gigabit Ethernet, SONET, Fibre Chan- nel 1 and 2, and Infiniband applications. FEATURES • 2 LVCMOS/LVTTL outputs • Selectable crystal oscillator interface or LVCMOS/LVTTL TEST_CLK • Output frequency range: 103.3MHz to 260MHz • Crystal input frequency range: 14MHz to 40MHz • VCO range: 620MHz to 780MHz • Parallel or serial interface for programming counter and output dividers • RMS period jitter: 4.3ps (typical) (N ÷ 4, VDDO = 3.3V ± 5%) • RMS phase jitter at 155.52MHz, using a 38.88MHz crystal (12KHz to 20MHz): 2.88ps (typical) Phase noise: 155.52MHz Offset Noise Power 100Hz ................. -93.7 dBc/Hz 1KHz ............... -111.3 dBc/Hz 10KHz ............... -120.4 dBc/Hz 100KHz ............... -125.1 dBc/Hz • Full 3.3V or mixed 3.3V core/2.5V or 1.8V supply voltage • 0°C to 70°C ambient operating temperature • Industrial temperature information available upon request BLOCK DIAGRAM PIN ASSIGNMENT OE0 OE1 VCO_SEL XTAL_SEL TEST_CLK XTAL1 XTAL2 OSC 0 1 MR S_LOAD S_DATA S_CLOCK nP_LOAD PLL PHASE DETECTOR VCO ÷M 0 1 ÷3 ÷4 ÷5 ÷6 CONFIGURATION INTERFACE LOGIC M5 M6 M7 M8 N0 N1 nc GND 32 31 30 29 28 27 26 25 1 24 2 23 3 22 4 ICS84021 21 5 20 6 19 7 18 8 17 9 10 11 12 13 14 15 16 XTAL2 TEST_CLK XTAL_SEL VDDA S_LOAD S_DATA S_CLOCK MR Q0 Q1 TEST 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View M0:M8 N0:N1 84021AY www.icst.com/products/hiperclocks.html 1 REV. A NOVEMBER 7, 2003 1 page Integrated Circuit Systems, Inc. ICS84021 260MHZ, CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE (PLL ENABLED) Inputs N1 N0 00 01 10 11 www.DataSheet4U.com N Divider Value 3 4 5 6 Output Frequency (MHz) Minimum Maximum 206.7 260 155 195 124 156 103.3 130 TABLE 3D. COMMONLY USED CONFIGURATION FUNCTION TABLE Crystal (MHz) 19.44 19.53125 25 25 25.50 25.50 25.50 38.88 Input M Divider Value 32 32 25 25 25 25 25 16 N Divider Value 4 4 4 5 3 4 6 4 Output Frequency (MHz) 155.52 156.25 156.25 125 212.50 159.375 106.25 155.52 TABLE 3E. OUTPUT ENABLE & CLOCK ENABLE FUNCTION TABLE Control Inputs OE0 OE1 00 01 10 11 Output Q0 Q1 Hi-Z Hi-Z Hi-Z Enabled Enabled Hi-Z Enabled Enabled 84021AY www.icst.com/products/hiperclocks.html 5 REV. A NOVEMBER 7, 2003 5 Page Integrated Circuit Systems, Inc. ICS84021 260MHZ, CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES www.DataSheetA4sU.icnomany high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS84021 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V , V , and V DD DDA DDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 24Ω resistor along with a 10µF and a .01µF bypass capacitor should be connected to each VDDA pin. V DD VDDA 3.3V .01µF 24Ω .01µF 10µF FIGURE 2. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE The ICS84021 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 3 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. X1 18pF Parallel Cry stal XTAL2 C1 22p XTAL1 C2 22p Figure 3. CRYSTAL INPUt INTERFACE 84021AY www.icst.com/products/hiperclocks.html 11 REV. A NOVEMBER 7, 2003 11 Page

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