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PDF ICS840002I Data sheet ( Hoja de datos )
| Número de pieza | ICS840002I | |
| Descripción | CRYSTAL-TO LVCMOS/LVTTL FREQUENCY SYNTHESIZER | |
| Fabricantes | Integrated Circuit Systems | |
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Integrated
Circuit
Systems, Inc.
ICS840002I
FEMTOCLOCKS™CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
The ICS840002I is a 2 output LVCMOS/LVTTL
ICS Synthesizer optimized to generate Fibre Channel
HiPerClockS™ reference clock frequencies and is a member of
the HiPerClocksTM family of high performance
clock solutions from ICS. Using a 26.5625MHz
18pF parallel resonant crystal, the following frequencies can be
generated based on the 2 frequency select pins (F_SEL1:0):
212.5MHz, 159.375MHz, 156.25MHz, 106.25MHz, and
www.DataShee5t43U.1.c2o5mMHz.The ICS840002I uses ICS’ 3rd generation low phase
noise VCO technology and can achieve 1ps or lower typical
rms phase jitter, easily meeting Fibre Channel jitter requirements.
The ICS840002I is packaged in a 16-pin TSSOP package.
FREQUENCY SELECT FUNCTION TABLE
FEATURES
• Two LVCMOS outputs @ 3.3V, 17Ω typical output impedance
• Selectable crystal oscillator interface
or LVCMOS single-ended input
• Output frequency range: 46.66MHz - 233.33MHz
• VCO range: 560MHz - 700MHz
• Supports the following output frequencies: 212.5MHz,
159.375MHz, 156.25MHz, 106.25MHz and 53.125MHz
• RMS phase jitter @ 212.5MHz (637KHz - 10MHz):
0.83ps (typical)
Typical phase noise at 212.5MHz:
Offset
Noise Power
100Hz ............... -91.3 dBc/Hz
1KHz .............. -114.3 dBc/Hz
10KHz .............. -120.7 dBc/Hz
100KHz .............. -120.2 dBc/Hz
• Power supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
• -40°C to 85°C ambient operating temperature
• Lead-Free package RoHS compliant
Input Frequency
(MHz)
26.5625
26.5625
26.5625
26.5625
26.04166
F_SEL1
0
0
1
1
0
F_SEL0
0
1
0
1
1
Inputs
M Divider Value N Divider Value
24 3
24 4
24 6
24 12
24 4
M/N Ratio Value
8
6
4
2
6
Output Frequency
(MHz)
212.5
159.375
106.25
53.125
156.25
BLOCK DIAGRAM
OE Pullup
F_SEL1:0 Pullup:Pullup
nPLL_SEL Pulldown
nXTAL_SEL Pulldown
XTAL_IN 26.5625MHz
OSC 0
XTAL_OUT
TEST_CLK Pulldown
1
2
Phase
Detector
VCO
F_SEL1:0
1N
0 0 ÷3
0 1 ÷4
0 1 0 ÷6
1 1 ÷12 (default)
M = ÷24 (fixed)
PIN ASSIGNMENT
F_SEL0 1 16 F_SEL1
nXTAL_SEL 2 15 GND
TEST_CLK 3 14 GND
OE 4 13 Q0
MR 5 12 Q1
nPLL_SEL 6
1 1 VDDO
VDDA 7
10 XTAL_IN
VDD 8
9 XTAL_OUT
Q0
ICS840002I
16-Lead TSSOP
Q1 4.4mm x 5.0mm x 0.92mm
package body
G Package
Top View
MR Pulldown
840002AGI
www.icst.com/products/hiperclocks.html
1
REV. A MARCH 10, 2005
1 page  
Integrated
Circuit
Systems, Inc.
ICS840002I
FEMTOCLOCKS™CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
TABLE 6A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical
F_SEL[1:0] = 00
186.67
fOUT Output Frequency Range
F_SEL[1:0] = 01
F_SEL[1:0] = 10
140
93.33
F_SEL[1:0] = 11
46.67
tsk(o) Output Skew; NOTE 1, 3
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tjit(Ø)
RMS Phase Jitter (Random);
NOTE 2
212.5MHz @ Integration Range:
637KHz - 10MHz
159.375MHz @ Integration Range:
637KHz - 10MHz
156.25MHz @ Integration Range:
1.875MHz - 20MHz
106.25MHz @ Integration Range:
637KHz - 10MHz
53.125MHz @ Integration Range:
637KHz - 10MHz
0.83
0.62
0.59
0.80
0.68
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
F_SEL[1:0] ≠ 00
F_SEL[1:0] = 00
200
46
42
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
Maximum
226.67
170
113.33
56.67
12
700
54
58
Units
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
%
%
TABLE
6B.
AC
CHARACTERISTICS,
V
DD
=
V
DDA
=
3.3V±5%,
V
DDO
=
2.5V±5%,
TA
=
-40°C
TO
85°C
Symbol Parameter
Test Conditions
Minimum Typical
F_SEL[1:0] = 00
186.67
fOUT Output Frequency Range
F_SEL[1:0] = 01
F_SEL[1:0] = 10
140
93.33
F_SEL[1:0] = 11
46.67
tsk(o) Output Skew; NOTE 1, 3
212.5MHz @ Integration Range:
637KHz - 10MHz
0.73
159.375MHz @ Integration Range:
637KHz - 10MHz
0.62
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 2
156.25MHz @ Integration Range:
1.875MHz - 20MHz
0.56
106.25MHz @ Integration Range:
637KHz - 10MHz
0.76
53.125MHz @ Integration Range:
637KHz - 10MHz
0.72
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
F_SEL[1:0] ≠ 00
F_SEL[1:0] = 00
200
46
42
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
Maximum
226.67
170
113.33
56.67
12
700
54
58
Units
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
%
%
840002AGI
www.icst.com/products/hiperclocks.html
REV. A MARCH 10, 2005
5
5 Page 
Integrated
Circuit
Systems, Inc.
ICS840002I
FEMTOCLOCKS™CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP
www.DataSheet4U.com
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
137.1°C/W
89.0°C/W
200
118.2°C/W
81.8°C/W
500
106.8°C/W
78.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS840002I is: 3085
840002AGI
www.icst.com/products/hiperclocks.html
11
REV. A MARCH 10, 2005
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet ICS840002I.PDF ] | |
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