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PDF CYW15G0403DXB Data sheet ( Hoja de datos )
| Número de pieza | CYW15G0403DXB | |
| Descripción | Transceiver | |
| Fabricantes | Cypress Semiconductor | |
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CYP15G0403DXB
CYV15G0403DXB
CYW15G0403DXB
Independent Clock Quad HOTLink II™
Transceiver
Features
• Second-generation HOTLink® technology
• Compliant to multiple standards
— ESCON, DVB-ASI, SMPTE-292M, SMPTE-259M, Fibre
Channel and Gigabit Ethernet (IEEE802.3z)
— CPRI™ compliant
www.DataSheet4U—.coCmYW15G0403DXB compliant to OBSAI-RP3
— 8B/10B coded data or 10 bit uncoded data
• Quad channel transceiver operates from 195 to
1500 MBaud serial data rate
— CYW15G0403DXB operates from 195 to 1540 MBaud
— Aggregate throughput of up to 12 Gbits/second
• Second-generation HOTLink technology
• Truly independent channels
— Each channel can operate at a different signaling rate
— Each channel can transport a different type of data
• Selectable input/output clocking options
• Internal phase-locked loops (PLLs) with no external PLL
components
• Dual differential PECL-compatible serial inputs per channel
• Internal DC-restoration
• Dual differential PECL-compatible serial outputs per
channel
— Source matched for 50Ω transmission lines
— No external bias resistors required
— Signaling-rate controlled edge-rates
• MultiFrame™ Receive Framer provides alignment options
— Bit and byte alignment
— Comma or Full K28.5 detect
— Single or Multi-byte Framer for byte alignment
— Low-latency option
• Synchronous LVTTL parallel interface
• JTAG boundary scan
• Built-In Self-Test (BIST) for at-speed link testing
• Compatible with
— Fiber-optic modules
— Copper cables
— Circuit board traces
• Per-channel Link Quality Indicator
— Analog signal detect
— Digital signal detect
• Low-power 3W @ 3.3V typical
• Single 3.3V supply
• 256-ball thermally enhanced BGA
• Pb-Free package option available
• 0.25μ BiCMOS technology
Functional Description
The CYP(V)15G0403DXB[1] Independent Clock Quad
HOTLink II™ Transceiver is a point-to-point or point-to-multi-
point communications building block enabling transfer of data
over a variety of high-speed serial links like optical fiber,
balanced, and unbalanced copper transmission lines. The
signaling rate can be anywhere in the range of 195 to 1500
MBaud per serial link. Each channel operates independently
with its own reference clock allowing different rates. Each
transmit channel accepts parallel characters in an Input
Register, encodes each character for transport, and then
converts it to serial data. Each receive channel accepts serial
data and converts it to parallel data, decodes the data into
characters, and presents these characters to an Output
Register. Figure 1 on page 2 illustrates typical connections
between independent host systems and corresponding
CYP(V)(W)15G0403DXB chips
The CYW15G0403DXB[1] operates from 195 to 1540 MBaud,
which includes operation at the OBSAI RP3 datarate of both
1536 MBaud and 768 MBaud.
The CYV15G0403DXB satisfies the SMPTE-259M and
SMPTE-292M compliance as per SMPTE EG34-1999 Patho-
logical Test Requirements.
As a second-generation HOTLink device, the
CYP(V)(W)15G0403DXB extends the HOTLink family with
enhanced levels of integration and faster data rates, while
maintaining serial-link compatibility (data, command, and
BIST) with other HOTLink devices. The transmit (TX) section
of the CYP(V)(W)15G0403DXB Quad HOTLink II consists of
four independent byte-wide channels. Each channel can
accept either 8-bit data characters or preencoded 10-bit trans-
mission characters. Data characters may be passed from the
Transmit Input Register to an integrated 8B/10B Encoder to
improve their serial transmission characteristics. These
encoded characters are then serialized and output from dual
Positive ECL (PECL) compatible differential transmission-line
drivers at a bit-rate of either 10 or 20 times the input reference
clock for that channel.
.
Note
1. CYV15G0403DXB refers to SMPTE 259M and SMPTE 292M compliant devices. CYW15G0403DXB refers to OBSAI RP3 compliant devices (maximum operating
data rate is 1540 MBaud). CYP15G0403DXB refers to devices not compliant to SMPTE 259M and SMPTE 292M pathological test requirements and also OBSAI
RP3 operating datarate of 1536 MBaud. CYP(V)(W)15G0403DXB refers to all three devices.
Cypress Semiconductor Corporation
Document #: 38-02065 Rev. *F
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Revised May 2, 2007
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1 page  
Receive Path Block Diagram
SPDSELA
RXPLLPDA
SDASELA[1:0]
LPENA
INSELA
INA1+
www.DataSheet4U.IcNoAm1–
INA2+
INA2–
TXLBA
ULCA
SPDSELB
RXPLLPDB
SDASELB[1:0]
LPENB
INSELB
INB1+
INB1–
INB2+
INB2–
TXLBB
ULCB
SPDSELC
RXPLLPDC
SDASELC[1:0]
LPENC
INSELC
INC1+
INC1–
INC2+
INC2–
TXLBC
ULCC
SPDSELD
RXPLLPDD
SDASELD[1:0]
LPEND
INSELD
IND1+
IND1–
IND2+
IND2–
TXLBD
ULCD
Receive
Signal
Monitor
Clock &
Data
Recovery
PLL
Receive
Signal
Monitor
Clock &
Data
Recovery
PLL
Receive
Signal
Monitor
Clock &
Data
Recovery
PLL
Receive
Signal
Monitor
Clock &
Data
Recovery
PLL
LDTDEN
RFMODE[A..D][1:0]
RFEN[A..D]
FRAMCHAR[A..D]
DECMODE[A..D]
RXBIST[A..D]
RXCKSEL[A..D]
DECBYP[A..D]
RXRATE[A..D]
Document #: 38-02065 Rev. *F
CYP15G0403DXB
CYV15G0403DXB
CYW15G0403DXB
TXLB[A..D] are Internal Serial Loopback Signals
= Internal Signal
JTAG
Boundary
Scan
Controller
RESET
TRST
TMS
TCLK
TDI
TDO
LFIA
8 RXDA[7:0]
3
RXSTA[2:0]
Clock
Select
÷2
8
3
RXCLKA+
RXCLKA–
LFIB
RXDB[7:0]
RXSTB[2:0]
Clock
Select
÷2
8
3
RXCLKB+
RXCLKB–
LFIC
RXDC[7:0]
RXSTC[2:0]
Clock
Select
÷2
8
3
RXCLKC+
RXCLKC–
LFID
RXDD[7:0]
RXSTD[2:0]
Clock
Select
÷2
RXCLKD+
RXCLKD–
Page 5 of 45
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5 Page 
CYP15G0403DXB
CYV15G0403DXB
CYW15G0403DXB
Pin Descriptions (continued)
CYP(V)(W)15G0403DXB Quad HOTLink II Transceiver
Name
I/O Characteristics Signal Description
LFIA
LFIB
LFIC
LFID
www.DataSheet4U.com
LVTTL Output,
asynchronous
Link Fault Indication Output. LFIx is an output status indicator signal. LFIx is the
logical OR of six internal conditions. LFIx is asserted LOW when any of the following
conditions is true:
• Received serial data rate outside expected range
• Analog amplitude below expected levels
• Transition density lower than expected
• Receive channel disabled
• ULCx is LOW
• Absence of REFCLKx±.
Device Configuration and Control Bus Signals
WREN
LVTTL input,
asynchronous,
internal pull-up
Control Write Enable. The WREN input writes the values of the DATA[7:0] bus into
the latch specified by the address location on the ADDR[3:0] bus.[5]
ADDR[3:0]
LVTTL input
asynchronous,
internal pull-up
Control Addressing Bus. The ADDR[3:0] bus is the input address bus used to
configure the device. The WREN input writes the values of the DATA[7:0] bus into the
latch specified by the address location on the ADDR[3:0] bus.[5] Table 9 on page 20
lists the configuration latches within the device, and the initialization value of the
latches upon the assertion of RESET. Table 10 on page 24 shows how the latches
are mapped in the device.
DATA[7:0]
LVTTL input
asynchronous,
internal pull-up
Control Data Bus. The DATA[7:0] bus is the input data bus used to configure the
device. The WREN input writes the values of the DATA[7:0] bus into the latch
specified by address location on the ADDR[3:0] bus.[5 ] Table 9 lists the configuration
latches within the device, and the initialization value of the latches upon the assertion
of RESET. Table 10 shows how the latches are mapped in the device.
Internal Device Configuration Latches
RFMODE[A..D][1:0] Internal Latch[6]
Reframe Mode Select.
FRAMCHAR[A..D] Internal Latch[6]
Framing Character Select.
DECMODE[A..D] Internal Latch[6]
Receiver Decoder Mode Select.
DECBYP[A..D]
Internal Latch[6]
Receiver Decoder Bypass.
RXCKSEL[A..D] Internal Latch[6]
Receive Clock Select.
RXRATE[A..D]
Internal Latch[6]
Receive Clock Rate Select.
SDASEL[A..D][1:0] Internal Latch[6]
Signal Detect Amplitude Select.
ENCBYP[A..D]
Internal Latch[6]
Transmit Encoder Bypassed.
TXCKSEL[A..D] Internal Latch[6]
Transmit Clock Select.
TXRATE[A..D]
Internal Latch[6]
Transmit PLL Clock Rate Select.
RFEN[A..D]
Internal Latch[6]
Reframe Enable.
RXPLLPD[A..D] Internal Latch[6]
Receive Channel Power Control.
RXBIST[A..D]
Internal Latch[6]
Receive Bist Disabled.
TXBIST[A..D]
Internal Latch[6]
Transmit Bist Disabled.
OE2[A..D]
Internal Latch[6]
Differential Serial Output Driver 2 Enable.
OE1[A..D]
Internal Latch[6]
Differential Serial Output Driver 1 Enable.
Notes
5. See “Device Configuration and Control Interface” on page 20 for detailed information on the operation of the Configuration Interface.
6. See “Device Configuration and Control Interface” on page 20 for detailed information on the internal latches.
Document #: 38-02065 Rev. *F
Page 11 of 45
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