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PDF CYW15G0101DXB Data sheet ( Hoja de datos )
| Número de pieza | CYW15G0101DXB | |
| Descripción | Single-channel HOTLink Transceiver | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CYP15G0101DXB
CYV15G0101DXB
CYW15G0101DXB
Single-channel HOTLink II™ Transceiver
Features
• Second-generation HOTLink® technology
• Compliant to multiple standards
— ESCON®, DVB-ASI, Fibre Channel and Gigabit
Ethernet (IEEE802.3z)
— CPRI™ compliant
www.DataSheet4U—.coCmYW15G0101DXB compliant to OBSAI-RP3
— CYV15G0101DXB compliant to SMPTE 259M and
SMPTE 292M
— 8B/10B encoded or 10-bit unencoded data
• Single-channel transceiver operates from 195 to
1500 MBaud serial data rate
— CYW15G0101DXB operates from 195 to 1540 MBaud
• Selectable parity check/generate
• Selectable input clocking options
• Selectable output clocking options
• MultiFrame™ Receive Framer
— Bit and Byte alignment
— Comma or full K28.5 detect
— Single- or Multi-Byte framer for byte alignment
— Low-latency option
• Synchronous LVTTL parallel input and parallel output
interface
• Internal phase-locked loops (PLLs) with no external
PLL components
• Dual differential PECL-compatible serial inputs
— Internal DC-restoration
• Dual differential PECL-compatible serial outputs
— Source matched for driving 50Ω transmission lines
— No external bias resistors required
— Signaling-rate controlled edge-rates
• Optional Elasticity Buffer in Receive Path
• Optional Phase Align Buffer in Transmit Path
• Compatible with
— Fiber-optic modules
— Copper cables
— Circuit board traces
• JTAG boundary scan
• Built-In Self-Test (BIST) for at-speed link testing
• Per-channel Link Quality Indicator
— Analog signal detect
— Digital signal detect
• Low power 1.25W @ 3.3V typical
• Single 3.3V supply
• 100-ball BGA
• Pb-Free package option available
• 0.25µ BiCMOS technology
Functional Description
The CYP(V)15G0101DXB[1] single-channel HOTLink II™
transceiver is a point-to-point communications building block
allowing the transfer of data over a high-speed serial link
(optical fiber, balanced, and unbalanced copper transmission
lines) at signaling speeds ranging from 195 to 1500 MBaud.
The transmit channel accepts parallel characters in an Input
Register, encodes each character for transport, and converts
it to serial data. The receive channel accepts serial data and
converts it to parallel data, frames the data to character bound-
aries, decodes the framed characters into data and special
characters, and presents these characters to an Output
Register. Figure 1 illustrates typical connections between
independent host systems and corresponding
CYP(V)(W)15G0101DXB parts. As a second-generation
HOTLink device, the CYP(V)(W)15G0101DXB extends the
HOTLink II family with enhanced levels of integration and
faster data rates, while maintaining serial-link compatibility
(data, command, and BIST) with other HOTLink devices.
10
10
Serial Link
Backplane or Cabled
Connections
10
10
Note:
Figure 1. HOTLink II System Connections
1. CYV15G0101DXB refers to SMPTE 259M and SMPTE 292M compliant devices. CYW15G0101DXB refers to OBSAI RP3 compliant devices (maximum
operating data rate is 1540 MBaud). CYP15G0101DXB refers to devices not compliant to SMPTE 259M and SMPTE 292M pathological test requirements and
also OBSAI RP3 operating datarate of 1536 MBaud. CYP(V)(W)15G0101DXB refers to all three devices.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-02031 Rev. *J
Revised March 24, 2005
1 page  
CYP15G0101DXB
CYV15G0101DXB
CYW15G0101DXB
Pin Descriptions CYP(V)(W)15G0101DXB Single-channel HOTLink II
Pin Name I/O Characteristics Signal Description
Transmit Path Data Signals
TXPER
LVTTL Output,
changes relative to
REFCLK↑[3]
Transmit Path Parity Error. Active HIGH. Asserted (HIGH) if parity checking is enabled
(PARCTL ≠ LOW) and a parity error is detected at the Encoder. This output is HIGH for one
transmit character-clock period to indicate detection of a parity error in the character
presented to the Encoder.
If a parity error is detected, the character in error is replaced with a C0.7 character to force
a corresponding bad-character detection at the remote end of the link. This replacement
takes place regardless of the encoded/un-encoded state of the interface.
www.DataSheet4U.com
When BIST is enabled for the specific transmit channel, BIST progress is presented on this
output. Once every 511 character times (plus a 16-character Word Sync Sequence when
the receive channel is clocked by REFCLK, i.e., RXCKSEL = LOW), the TXPER signal
pulses HIGH for one transmit-character clock period (if RXCKSEL = MID) or seventeen
transmit-character clock periods (if RXCKSEL = LOW or HIGH) to indicate a complete pass
through the BIST sequence. For RXCKSEL = LOW or HIGH, If TXMODE[1:0] = LL, then no
Word Sync Sequence is sent in BIST, and TXPER pulses HIGH for one transmit-character
clock period.
This output also provides an indication of a Phase-Align Buffer underflow/overflow
condition. When the Phase-Align Buffer is enabled (TXCKSEL ≠ LOW, or TXCKSEL = LOW
and TXRATE = HIGH), and an underflow/overflow condition is detected, TXPER is asserted
and remains asserted until either an atomic Word Sync Sequence is transmitted or TXRST is
sampled LOW to recenter the Phase-Align Buffer.
TXCT[1:0]
LVTTL Input,
Transmit Control. These inputs are captured on the rising edge of the transmit interface
synchronous,
clock as selected by TXCKSEL, and are passed to the Encoder or Transmit Shifter. They
sampled by TXCLK↑ identify how the TXD[7:0] characters are interpreted. When the Encoder is enabled, these
or REFCLK↑[3]
inputs determine if the TXD[7:0] character is encoded as Data, a Special Character code,
a K28.5 fill character or a Word Sync Sequence. When the Encoder is bypassed, these
inputs are interpreted as data bits. See Table 1 for details.
TXD[7:0]
LVTTL Input,
Transmit Data Inputs. These inputs are captured on the rising edge of the transmit
synchronous,
interface clock as selected by TXCKSEL, and passed to the Encoder or Transmit Shifter.
sampled by TXCLK↑
or REFCLK↑[3]
When the Encoder is enabled (TXMODE[1] ≠ LOW), TXD[7:0] specify the specific data or
command character to be sent. When the Encoder is bypassed, these inputs are interpreted
as data bits of the 10-bit input character. See Table 1 for details.
TXOP
LVTTL Input,
Transmit Path Odd Parity. When parity checking is enabled (PARCTL ≠ LOW), the parity
synchronous,
captured at this input is XORed with the data on the TXD bus (and sometimes TXCT[1:0])
internal pull-up,
to verify the integrity of the captured character. See Table 2 for details.
sampled by TXCLK↑
or REFCLK↑[3]
SCSEL
LVTTL Input,
Special Character Select. Used in some transmit modes along with TXCTx[1:0] to encode
synchronous,
special characters or to initiate a Word Sync Sequence. When the transmit path is
internal pull-down, configured to select TXCLK to clock the input register (TXCKSEL = MID or HIGH), SCSEL
sampled by TXCLK↑ is captured relative to TXCLK↑.
or REFCLK↑[3]
Note:
3. When REFCLK is configured for half-rate operation (TXRATE = HIGH), this input is sampled (or the outputs change) relative to both the rising and falling edges
of REFCLK.
Document #: 38-02031 Rev. *J
Page 5 of 39
5 Page 
CYP15G0101DXB
CYV15G0101DXB
CYW15G0101DXB
CYP(V)(W)15G0101DXB HOTLink II Operation
The CYP(V)(W)15G0101DXB is a highly configurable device
designed to support reliable transfer of large quantities of data
using high-speed serial links from a single source to one or
more destinations.
CYP(V)(W)15G0101DXB Transmit Data Path
Operating Modes
The transmit path of the CYP(V)(W)15G0101DXB supports a
single character-wide data path. This data path is used in
multiple operating modes as controlled by the TXMODE[1:0]
inputs.
www.DataSheetI4nUp.uctoRmegister
The bits in the Input Register support different assignments,
based on if the character is unencoded, encoded with two
control bits, or encoded with three control bits. These assign-
ments are shown in Table 1.
Table 1. Input Register Bit Assignments[5]
Signal Name
TXD[0] (LSB)
TXD[1]
Unencoded
(Encoder
Bypassed)
DIN[0]
DIN[1]
Encoded
(Encoder Enabled)
Two-bit
Control
Three-bit
Control
TXD[0]
TXD[0]
TXD[1]
TXD[1]
TXD[2]
DIN[2]
TXD[2]
TXD[2]
TXD[3]
DIN[3]
TXD[3]
TXD[3]
TXD[4]
TXD5]
TXD[6]
DIN[4]
DIN[5]
DIN[6]
TXD[4]
TXD[5]
TXD[6]
TXD[4]
TXD[5]
TXD[6]
TXD[7]
DIN[7]
TXD[7]
TXD[7]
TXCT[0]
TXCT[1] (MSB)
SCSEL
DIN[8]
DIN[9]
N/A
TXCT[0]
TXCT[1]
N/A
TXCT[0]
TXCT[1]
SCSEL
The Input Register captures a minimum of eight data bits and
two control bits on each input clock cycle. When the Encoder
is bypassed, the TXCT[1:0] control bits are part of the
pre-encoded 10-bit data character.
When the Encoder is enabled (TXMODE[1] ≠ LOW), the
TXCT[1:0] bits are interpreted along with the TXD[7:0]
character to generate the specific 10-bit transmission
character. When TXMODE[0] ≠ HIGH, an additional special
character select (SCSEL) input is also captured and inter-
preted. This SCSEL input is used to modify the encoding of the
characters.
Phase-Align Buffer
operated synchronous to REFCLK↑ (TXCKSEL = LOW and
TXRATE = LOW), the Phase-Align Buffer is bypassed and
data is passed directly to the Parity Check and Encoder block
to reduce latency.
When an Input Register clock with an uncontrolled phase
relationship to REFCLK is selected (TXCKSEL ≠ LOW) or if
data is captured on both edges of REFCLK
(TXRATE = HIGH), the Phase-Align Buffer is enabled. This
buffer is used to absorb clock phase differences between the
presently selected input clock and the internal character clock.
Initialization of the Phase-Align Buffer takes place when the
TXRST input is sampled LOW by two consecutive rising edges
of REFCLK. When TXRST is returned HIGH, the present input
clock phase relative to REFCLK↑ is set. TXRST is an
asynchronous input, but is sampled internally to synchronize
it to the internal transmit path state machine.
Once set, the input clock is allowed to skew in time up to half
a character period in either direction relative to REFCLK↑;
i.e., ±180°. This time shift allows the delay path of the
character clock (relative to REFLCK↑) to change due to
operating voltage and temperature, while not affecting the
design operation.
If the phase offset, between the initialized location of the input
clock and REFCLK↑, exceeds the skew handling capabilities
of the Phase-Align Buffer, an error is reported on the TXPER
output. This output indicates a continuous error until the
Phase-Align Buffer is reset. While the error remains active, the
transmitter outputs a continuous C0.7 character to indicate to
the remote receiver that an error condition is present in the
link.
In specific transmit modes, it is also possible to reset the
Phase-Align Buffer with minimal disruption of the serial data
stream. When the transmit interface is configured for gener-
ation of atomic Word Sync Sequences (TXMODE[1] = MID)
and a Phase-Align Buffer error is present, the transmission of
a Word Sync Sequence will recenter the Phase-Align Buffer
and clear the error condition.[6]
Parity Support
In addition to the ten data and control bits that are captured at
the transmit Input Register, a TXOP input is also available.
This allows the CYP(V)(W)15G0101DXB to support ODD
parity checking. Parity checking is available for all operating
modes (including Encoder Bypass). The specific mode of
parity checking is controlled by the PARCTL input, and
operates per Table 2.
When PARCTL = MID (open) and the Encoder is enabled
(TXMODE[1] ≠ LOW), only the TXD[7:0] data bits are checked
for ODD parity along with the TXOP bit. When
PARCTL = HIGH with the Encoder enabled (or MID with the
Encoder bypassed), the TXD[7:0] and TXCT[1:0] inputs are
checked for ODD parity along with the TXOP bit. When
PARCTL = LOW, parity checking is disabled.
Data from the Input Register is passed either to the Encoder
or to the Phase-Align buffer. When the transmit path is
Notes:
5. The TXOP input is also captured in the Input Register, but its interpretation is under the separate control of PARCTL.
6. One or more K28.5 characters may be added or lost from the data stream during this reset operation. When used with non-Cypress devices that require a
complete 16-character Word Sync Sequence for proper receive Elasticity Buffer alignment, it is recommend that the sequence be followed by a second Word
Sync Sequence to ensure proper operation.
Document #: 38-02031 Rev. *J
Page 11 of 39
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