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PDF AM79C850 Data sheet ( Hoja de datos )
| Número de pieza | AM79C850 | |
| Descripción | SUPERNET 3 | |
| Fabricantes | AMD | |
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PRELIMINARY
Am79C850
SUPERNET® 3
Advanced
Micro
Devices
DISTINCTIVE CHARACTERISTICS
s Compliant with the ANSI X3T9.5/ISO 9314
specification
— 100 Mbps data rate
— Timed token-passing protocol
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— Ring topology
s Complete memory management
— Supports 256K bytes of local frame buffer
memory
— Supports buffer memory bandwidths of
200 Mbps and 400 Mbps
— Tag-Mode: minimum latency/highest
performance buffer memory management, ideal
for adapter card designs
FUNCTIONAL OVERVIEW
SUPERNET 3 is a 208-pin CMOS integration of FDDI
MAC, PHY, Address Filter, and clock generation and
recovery functions. It is the third generation FDDI
offering from AMD which integrates the SUPERNET 2
family of chips into a single-chip solution. Refer to the
SUPERNET 2 data book (PID 15502C) for basic
feature descriptions.
The SUPERNET 3 is backward compatible to the
SUPERNET 2 Tag Mode of operation in which the
SUPERNET 3 buffer memory interface logic maintains
the buffer memory as multiple FIFOs.
The SUPERNET 3 provides DMA channels, arbitrates
access to the network buffer memory, and controls the
data path between the buffer memory and the medium.
The MAC also implements the timed-token protocol and
receive/transmit control as specified for the Media
Access Control (MAC) sublayer of the ISO standard
9314-2 for FDDI. The Physical Layer functions defined
by the ISO 9314-1 are performed by the SUPERNET 3.
SUPERNET 3 implements on-chip digital clock
recovery and transmit functions for fiber. To support
copper media, the PHY-PMD interface is maintained
and an external module can be implemented in
the same footprint as the fiber optic transceiver to
perform the MLT-3 encoding/decoding and equaliza-
tion. SUPERNET 3 integrates the scrambler and
descrambler functions for transmissions over
copper media.
s ANSI-compliant TP-PMD Stream Cipher
Scrambling/Descrambling
s Full duplex operation: 200 Mbps continuous
data rate
s Supports both fiber optic and copper twisted-
pair media
s Diagnostic features
— Built in Self Test (BIST) in Address Filter,
Physical Layer Controller with Scrambler
s Hardware Physical Connection Management
support
s Low power consumption—reduction of more
than 25% from SUPERNET 2 solution
SUPERNET 3 FEATURES UPDATE
The basic feature description for SUPERNET 3 is
provided in the SUPERNET 2 data book. The enhanced
features are as listed below:
s This is a CMOS integration of the redesigned
FORMAC Plus, an enhanced PLC, a 32-entry
address filter (AF, which is based on a Content
Addressable Memory, or CAM, core), and a CMOS
PDX core for clock and data recovery.
s A 32-entry, extensible and fully maskable AF
allows additional individual and group addresses to
be supported.
s The physical data transmitter and receiver (PDX)
circuits are also embedded on-chip using
proprietary digital clock-recovery technology.
s For the purposes of implementing copper PMD,
the scrambler/descrambler functions are
embedded within the chip.
s The Buffer Memory interface has been modified to
support slower SRAM’s (35 ns) without affecting
backward compatibility with SUPERNET 2.
s SUPERNET 3 supports the FDDI single
attachment station (SAS) but is capable of
supporting a dual attachment station (DAS)
This document contains information on a product under development at Advanced Micro Devices, Inc. The information is intended Publication# 19574 Rev. A Amendment /0
to help you to evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Issue Date: April 1995
1 page  
Table of Contents (continued)
PRELIMINARY
AMD
Address Filter Test Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Test Logic Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Writing Entries into the AF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Finding Entries in the AF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Invalidating Entries in the AF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
PDX Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Default Timer and Register Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
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SUPERNET 3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
SUPERNET 3 Programmable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
SUPERNET 3 Command Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
SUPERNET 3 Command Registers 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
SUPERNET 3 Command Registers 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Revision I.D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
DC CHARACTERISTICS over operating ranges unless otherwise specified . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
PHY Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
MAC Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Testability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
PQR208, Trimmed and Formed
208-Pin Plastic Quad Flat Pack (measured in inches) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
SUPERNET 3
5
5 Page 
PRELIMINARY
AMD
PIN DESCRIPTION
I/O pins can only be high impedance in Test Access Port
(TAP) operation. Refer to TAP Testability section.
PHY/PMD Interface (46 Pins)
RX+, RX-
Receive Data (PECL Input)
These pins receive differential NRZI data.
TX+, TX-
Transmit Data (PECL Output)
These transmit outputs carry differential NRZI data.
They can be forced to logical 0 (TX+ LOW, TX- HIGH) by
asserting the FOTOFF input.
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RCU
Receive Control Upper (TTL input)
RCU is asserted high to indicate that the upper nibble of
the R bus (R7–4) is a network control character. When
RCU is low, this nibble contains data. RCU is synchro-
nous to BCLK. This pin has internal pull-up.
RCL
Receive Control Lower (TTL input)
RCL is asserted high to indicate that the lower nibble of
the R bus (R3–0) is a network control character. When
RCL is low, this nibble contains data. RCL is synchro-
nous to BCLK. This pin has internal pull-up.
R7–0
Receive Bus (TTL input)
The R bus is used to receive information from the
external physical layer (PHY) device. Bytes clocked
from the physical layer (PHY) into the SUPERNET 3
R-bus input are synchronous to the BCLK. These pins
have internal pull-up.
RPAR
Receive parity (TTL input)
RPAR is an input signal used to enhance error detection
on the external PHY interface R7:0 bus. RPAR is an
input signal used to implement even parity checking on
R bus. If there is an odd number of 1’s on {R7:0, RCU,
RCL}, then RPAR should be 1 and if there is an even
number of 1’s on {R7:0, RCU, RCL} then RPAR should
be 0. This pin has internal pull-up.
RXAFU3–0
Receive Bus Tap for External AF (TTL output, high
impedance)
The internal MAC Receive bus lines upper nibble are
tapped and brought out as the RXAFU 3–0 pins. These
pins are used by an external AF to do external SA and/or
DA match.
RXAFL3–0
Receive Bus Tap for External AF (TTL output, TTL
input, high impedance)
The internal MAC Receive bus lines lower nibble are
tapped and brought out as the RXAFL 3–0 pins. These
pins are used by an external AF to do external SA and/or
DA match.
Note: The RXAFL[3:0] input pins are for diagnostic
purposes only.
RXAFCU
Control Upper for AF Receive Bus (TTL output,
high impedance)
The RXAFCU output signal is used to flag control
symbols being presented on the nibble (3:0) of the
RXAFU bus. This signal is synchronous to BCLK. If
RXAFCU is asserted high, the nibble on the RXAFU bus
is interpreted as a network control character. Otherwise,
it is interpreted as a data nibble.
RXAFCL
Control Lower for AF Receive Bus (TTL output,
TTL input, high impedance)
The RXAFCL output signal is used to flag control
symbols being presented on the nibble (3:0) of the
RXAFL bus. This signal is synchronous to BCLK. If
RXAFCL is asserted high, the nibble on the RXAFL bus
is interpreted as a network control character. Otherwise,
it is interpreted as a data nibble.
Note: The RXAFCL input is for diagnostic
purposes only.
X7–0
Transmit Bus (TTL output, high impedance)
This eight-bit output bus is used to send control and data
information to the external physical layer (PHY) device
to be transmitted over the medium. Information on the
X-bus output is synchronous to the BCLK.
XPAR
Transmit parity (TTL output, high impedance)
XPAR is an output signal used to enhance error
detection on the MAC—external PHY interface X7:0
bus. If there is an odd number of 1’s on {X7:0, XCU,
XCL}, then XPAR should be 1 and if there is an even
number of 1’s on {X7:0, XCU, XCL} then XPAR should
be 0.
XCU
Transmit Control Upper (TTL output, high
impedance)
The XCU output signal is used to flag control symbols
being presented on the upper nibble of the transmit bus.
This signal is synchronous to BCLK. If XCU is asserted
SUPERNET 3
11
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| PDF Descargar | [ Datasheet AM79C850.PDF ] | |
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