PDF CY9C62256 Data sheet ( Hoja de datos )

Número de pieza	CY9C62256
Descripción	32K X 8 Magnetic Nonvolatile CMOS RAM
Fabricantes	Cypress Semiconductor
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No Preview Available ! PRELIMINARY CY9C62256 32K x 8 Magnetic Nonvolatile CMOS RAM Features • 100% Form, Fit, Function-compatible with 32K × 8, micropower SRAM (CY62256). — Fast Read and Write access: 70 ns — Voltage range: 4.5V–5.5V operation — Low active power: 495 mW (max.) www.DataSheet4U—.coLmow standby power, CMOS: 825 µW (max.) — Data retention current: 0 µA at VCC = 0V — Easy memory expansion with CE and OE features — TTL-compatible inputs and outputs — Automatic power-down when deselected • Replaces 32K × 8 Battery Backed (BB)SRAM, EEPROM, FeRAM or Flash memory — Data is automatically protected during power loss — Write Cycles Endurance: > 1015 Cycles — Data Retention: > 10 Years — Shielded from external magnetic fields — Extra 64 Bytes for Device Identification and tracking • Optional industrial temperature range: –40°C to +85°C • JEDEC STD 28-pin DIP (600-mil), 28-pin (300-mil) SOIC and TSOP packages Logic Block Diagram A11 A10 A9 A8 A7 A6 A3 A2 A1 CE WE OE INPUTBUFFER Silicon Sig. 512x512 ARRAY COLUMN DECODER POWER DOWN & WRITE PROTECT Description The CY9C62256 is a high-performance CMOS nonvolatile RAM employing an advanced magnetic RAM (MRAM) process. An MRAM is nonvolatile memory that operates as a RAM. It provides data retention for more than 10 years while eliminating the reliability concerns, functional disadvantages and system design complexities of battery-backed SRAM, EEPROM, Flash and FeRAM. Its fast writes and high write cycle endurance makes it superior to other types of nonvolatile memory. The CY9C62256 operates very similarly to other SRAM devices. Memory read and write cycles require equal times. The MRAM memory is nonvolatile due to its unique magnetic process. Unlike BBSRAM, the CY9C62256 is truly a monolithic nonvolatile memory. It provides the same functional benefits of a fast write without the serious disadvantages associated with modules and batteries or hybrid memory solutions. These capabilities make the CY9C62256 ideal for nonvolatile memory applications requiring frequent or rapid writes in a bytewide environment. The CY9C62256 is offered in both commercial and industrial temperature ranges. I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 OE A1 A2 A3 A4 WE VCC A5 A6 A7 A8 A9 A10 A11 Pin Configurations SOIC/DIP Top View A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 VCC 27 WE 26 A4 25 A3 24 A2 23 A1 22 OE 21 A0 20 CE 19 18 I/O7 I/O6 17 I/O5 16 I/O4 15 I/O3 22 21 A0 23 20 CE 24 19 I/O7 25 18 I/O6 26 17 I/O5 27 TSOP I 16 I/O4 28 Top View 15 I/O3 1 (not to scale) 14 GND 2 13 I/O2 3 12 I/O1 4 11 I/O0 5 10 A14 6 9 A13 7 8 A12 Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Document # 38-15001 Rev. B Revised June 21, 2002 1 page PRELIMINARY Switching Characteristics Over the Operating Range[5] Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE www.DataSheet4tHUZ.OcoEm tLZCE tHZCE tPU tPD Write Cycle[8,9] tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Description Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z[6] OE HIGH to High Z[6,7] CE LOW to Low Z[6] CE HIGH to High Z[6,7] CE LOW to Power-up CE HIGH to Power-down Write Cycle Time CE LOW to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-up to Write End Data Hold from Write End WE LOW to High Z[6, 7] WE HIGH to Low Z[6] Switching Waveforms Read Cycle No. 1[10, 11] ADDRESS DATA OUT tOHA PREVIOUS DATA VALID tAA tRC CY9C62256 CY9C62256-70 Min. Max. 70 70 5 70 35 5 25 5 25 0 70 70 60 60 0 0 50 30 0 25 5 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns DATA VALID Notes: 5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 100-pF load capacitance. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 9. The minimum write pulse width for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 10. Device is continuously selected. OE, CE = VIL. 11. WE is HIGH for read cycle. Document # 38-15001 Rev. B Page 5 of 10 5 Page

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