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PDF M12L2561616A Data sheet ( Hoja de datos )
| Número de pieza | M12L2561616A | |
| Descripción | 6 Bit x 4 Banks Synchronous DRAM | |
| Fabricantes | Elite Semiconductor | |
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ESMT
SDRAM
FEATURES
y JEDEC standard 3.3V power supply
y LVTTL compatible with multiplexed address
y Four banks operation
y MRS cycle with address key programs
- CAS Latency ( 2 & 3 )
www.DataSheet-4UB.ucrosmt Length ( 1, 2, 4, 8 & full page )
- Burst Type ( Sequential & Interleave )
y All inputs are sampled at the positive going edge of the
system clock
y Burst Read single write operation
y DQM for masking
y Auto & self refresh
y 64ms refresh period (8K cycle)
M12L2561616A
4M x 16 Bit x 4 Banks
Synchronous DRAM
ORDERING INFORMATION
PRODUCT NO. MAX FREQ. PACKAGE COMMENTS
M12L2561616A-6TG 166MHz TSOP II
Pb-free
M12L2561616A-6BG 166MHz
BGA
Pb-free
M12L2561616A-7TG 143MHz TSOP II
Pb-free
M12L2561616A-7BG 143MHz
BGA
Pb-free
GENERAL DESCRIPTION
The M12L2561616A is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 4,194,304 words by 16 bits.
Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a
variety of high bandwidth, high performance memory system applications.
Pin Arrangement
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
LDQM
WE
CAS
RAS
CS
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54 VSS
53 DQ15
52 VSSQ
51 DQ14
50 DQ13
49 VDDQ
48 DQ12
47 DQ11
46 VSSQ
45 DQ10
44 DQ9
43 VDDQ
42 DQ8
41 VSS
40 NC
39 UDQM
38 CLK
37 CKE
36 A12
35 A11
34 A9
33 A8
32 A7
31 A6
30 A5
29 A4
28 VSS
123 4567 89
A VSS DQ15 VSSQ
VDDQ DQ0 VDD
B DQ14 DQ13 VDDQ
C DQ12 DQ11 VSSQ
VSSQ DQ2 DQ1
VDDQ DQ4 DQ3
D DQ10 DQ9 VDDQ
VSSQ DQ6 DQ5
E
DQ8
NC
VSS
VDD LDQM DQ7
F UDQM CLK CKE
G
A12 A11
A9
CAS RAS
WE
BA0 BA1 CS
H A8 A7 A6
J
VSS
A5
A4
A0 A1 A10
A3 A2 VDD
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2007
Revision: 1.2
1/44
1 page  
ESMT
M12L2561616A
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V ，TA = 0 to 70 °C )
Parameter
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall-time
Output timing measurement reference level
Output load condition
Value
2.4/0.4
1.4
tr/tf = 1/1
1.4
See Fig. 2
Unit
V
V
ns
V
www.DataSheet4U.com
(Fig. 1) DC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Symbol
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
@ Operating
@ Auto refresh
Last data in to col. address delay
Last data in to row precharge
Last data in to burst stop
Refresh period (8,192 rows)
tRRD(min)
tRCD(min)
tRP(min)
tRAS(min)
tRAS(max)
tRC(min)
tRFC(min)
tCDL(min)
tRDL(min)
tBDL(min)
tREF(max)
(Fig. 2) AC Output Load Circuit
Version
-6 -7
12 14
18 20
18 20
42 45
100
60 63
60 70
1
2
1
64
Unit
ns
ns
ns
ns
us
ns
ns
tCK
tCK
tCK
ms
Note
1
1
1
1
1
1,5
2
2
2
6
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2007
Revision: 1.2
5/44
5 Page 
ESMT
DEVICE OPERATIONS (Continued)
dividing tRCD(min) with cycle time of the clock and then rounding
of the result to the next higher integer. The SDRAM has four
internal banks in the same chip and shares part of the internal
circuitry to reduce chip area, therefore it restricts the activation
of four banks simultaneously. Also the noise generated during
sensing of each bank of SDRAM is high requiring some time
for power supplies to recover before another bank can be
sensed reliably. tRRD(min) specifies the minimum time required
between activating different bank. The number of clock cycles
required between different bank activation must be calculated
similar to tRCD specification. The minimum time required for the
bank to be active to initiate sensing and restoring the complete
www.DataShreoewt4Uof.cdoymnamic cells is determined by tRAS(min). Every SDRAM
bank activate command must satisfy tRAS(min) specification
before a precharge command to that active bank can be
asserted. The maximum time any bank can be in the active
state is determined by tRAS (max) and tRAS(max) can be
calculated similar to tRCD specification.
BURST READ
The burst read command is used to access burst of data on
consecutive clock cycles from an active row in an active bank.
The burst read command is issued by asserting low on CS
and RAS with WE being high on the positive edge of the
clock. The bank must be active for at least tRCD(min) before the
burst read command is issued. The first output appears in CAS
latency number of clock cycles after the issue of burst read
command. The burst length, burst sequence and latency from
the burst read command is determined by the mode register
which is already programmed. The burst read can be initiated
on any column address of the active row. The address wraps
around if the initial address does not start from a boundary
such that number of outputs from each I/O are equal to the
burst length programmed in the mode register. The output
goes into high-impedance at the end of burst, unless a new
burst read was initiated to keep the data output gapless. The
burst read can be terminated by issuing another burst read or
burst write in the same bank or the other active bank or a
precharge command to the same bank. The burst stop
command is valid at every page burst length.
BURST WRITE
The burst write command is similar to burst read command
and is used to write data into the SDRAM on consecutive clock
cycles in adjacent addresses depending on burst length and
burst sequence. By asserting low on CS , CAS and WE
with valid column address, a write burst is initiated. The data
inputs are provided for the initial address in the same clock
cycle as the burst write command. The input buffer is
deselected at the end of the burst length, even though the
internal writing can be completed yet. The writing can be
complete by issuing a burst read and DQM for blocking data
inputs or burst write in the same or another active bank. The
burst stop command is valid at every burst length. The write
burst can also be terminated by using DQM for blocking data
and precharge the bank tRDL after the last data input to be
written into the active row. See DQM OPERATION also.
Elite Semiconductor Memory Technology Inc.
M12L2561616A
DQM OPERATION
The DQM is used mask input and output operations. It
works similar to OE during operation and inhibits writing
during write operation. The read latency is two cycles from
DQM and zero cycle for write, which means DQM masking
occurs two cycles later in read cycle and occurs in the
same cycle during write cycle. DQM operation is
synchronous with the clock. The DQM signal is important
during burst interrupts of write with read or precharge in
the SDRAM. Due to asynchronous nature of the internal
write, the DQM operation is critical to avoid unwanted or
incomplete writes when the complete burst write is
required. Please refer to DQM timing diagram also.
PRECHARGE
The precharge is performed on an active bank by
asserting low on clock cycles required between bank
activate and clock cycles required between bank activate
and CS , RAS , WE and A10/AP with valid BA0~BA1
of the bank to be procharged. The precharge command
can be asserted anytime after tRAS(min) is satisfy from the
bank active command in the desired bank. tRP is defined
as the minimum number of clock cycles required to
complete row precharge is calculated by dividing tRP with
clock cycle time and rounding up to the next higher
integer. Care should be taken to make sure that burst
write is completed or DQM is used to inhibit writing before
precharge command is asserted. The maximum time any
bank can be active is specified by tRAS(max). Therefore,
each bank has to be precharge with tRAS(max) from the
bank activate command. At the end of precharge, the
bank enters the idle state and is ready to be activated
again. Entry to power-down, Auto refresh, Self refresh and
Mode register set etc. is possible only when all banks are
in idle state.
AUTO PRECHARGE
The precharge operation can also be performed by using
auto precharge. The SDRAM internally generates the
timing to satisfy tRAS(min) and “tRP” for the programmed burst
length and CAS latency. The auto precharge command is
issued at the same time as burst write by asserting high on
A10/AP, the bank is precharge command is asserted.
Once auto precharge command is given, no new
commands are possible to that particular bank until the
bank achieves idle state.
FOUR BANKS PRECHARGE
Four banks can be precharged at the same time by using
Precharge all command. Asserting low on CS , RAS ,
and WE with high on A10/AP after all banks have
satisfied tRAS(min) requirement, performs precharge on all
banks. At the end of tRP after performing precharge all, all
banks are in idle state.
Publication Date: Aug. 2007
Revision: 1.2
11/44
11 Page | ||
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