PDF PI6CU877 Data sheet ( Hoja de datos )

Número de pieza	PI6CU877
Descripción	PLL Clock Driver
Fabricantes	Pericom Semiconductor Corporation
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No Preview Available ! PI6CU877 PLL Clock Driver for 1.8V DDR2 Memory Features • PLL clock distribution optimized for DDR2 SDRAM applications. • Distributes one differential clock input pair to ten differential clock output pairs. www.DataS•heDet4ifUfe.croemntial Inputs (CLK, CLK) and (FBIN, FBIN) • Input OE/OS: LVCMOS • Differential Outputs (Y[0:9], Y[0:9] and (FBOUT, FBOUT) • External feedback pins (FBIN, FBIN) are used to synchronize the outputs to the clock input. • Operates at AVDD = 1.8V for core circuit and internal PLL, and VDDQ = 1.8V for differential output drivers • Packaging (Pb-free & Green available): – 52-ball VFBGA (NF) Pin Configuration 1 A Y1 2 Y0 B Y1 GND C Y2 GND D Y2 VDDQ E CK VDDQ F CK VDDQ G AGND VDDQ H AVDD GND J Y3 GND k Y3 Y4 3 Y0 GND NB VDDQ NB NB VDDQ NB GND Y4 4 Y5 GND NB VDDQ NB NB VDDQ NB GND Y9 56 Y5 Y6 GND Y6 GND Y7 OS Y7 VDDQ FBIN OE FBIN VDDQ FBOUT GND FBOUT GND Y8 Y9 Y8 Description PI6CU877 PLL clock driver is developed for Registered DDR2 DIMM applications with 1.8V operation and differential data input and output levels. The device is a zero delay buffer that distributes a differential clock input pair (CLK, CLK) to eleven differential pairs of clock outputs which includes feedback clock (Y[0:9], Y[0:9]; FBOUT, FBOUT). The clock outputs are controlled by CLK/CLK, FBOUT, FBOUT, the LVCMOS (OE, OS) and the Analog Power input (AVDD). When OE is LOW the outputs except FBOUT, FBOUT, are disabled while the internal PLL continues to maintain its locked-in frequency. OS is a program pin that must be tied to GND or VDD. When OS is high, OE will function as described above. When OS is LOW, OE has no effect on Y7/Y7, they are free running. When AVDD is grounded, the PLL is turned off and bypassed for test purposes. When CLK/CLK are logic low, the device will enter a low power mode.An input logic detection circuit will detect the logic low level and perform a low power state where all Y[0:9], Y[0:9]; FBOUT, FBOUT, and PLL are OFF. PI6CU877 is a high performance, low skew, and low jitter PLL clock driver, and it is also able to track Spread Spectrum Clocking (SSC) for reduced EMI. 1 PS8689B 08/05/04 1 page PI6CU877 PLL Clock Driver for 1.8V DDR2 Memory Timing Requirements (Over recommended operating free-air temperature) Symbol FCK Decription Operation clock frequency(7, 8) Application clock frequency(7, 9) AVDD, VDDQ = 1.8V ±0.1V Min. Max. 25 300 160 270 tDC tL www.DataSheet4Ut.OcFoFm Input clock duty cycle Stabalization time(10) Device power down(10) 40 60 15 8 Units MHz % µs ns Notes: 7. The PLL is able to handle spread spectrum induced skew. 8. Operating clock frequency indicates a range over which the PLL is able to lock, but in which it is not required to meet the other timing parameters. (Used for low-speed debug). 9. Application clock frequency indicates a range over which the PLL must meet all timing parameters. 10. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power up . During normal operation, the stabilization time is also the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal when CK and CK go to a logic low state, enter the power-down mode and later return to active operation. CK and CK maybe left floating after they have been driven low for one complete clock cycle. DC Specifications Param- eter Description VIK All Inputs Test Condition II= -18mA VOH HIGH output voltage IOH = -100µA IODL VOD II IDDLD IDD CI CI(∆) IOH = -9mA Output disabled low current OE = L, VODL = 100mV Output differenital voltage, the magniture of the difference between the true and complimentary outputs, see fig. 9 for dimentions CK, CK OE, OS, FBIN, FBIN Static Supple current, IDDQ + IADD VI = VDDQ or GND VI = VDDQ or GND CK and CK = L Dynamic supply current, IDDQ + IADD, see note 6 for CPD calcula- tion CK and CK = 270MHz, all outputs are open (not connected to a PCB) CK, CK VI = VDDQ or GND FBIN, FBIN VI = VDDQ or GND CK, CK FBIN, FBIN VI = VDDQ or GND VI = VDDQ or GND AVDD, VDDQ 1.7V 1.7 to 1.9V 1.7 1.7V 1.9V 1.8V Min. VDDQ -0.2 1.1 100 0.6 2 2 Typ. Max. Units 1.2 V ±250 ±10 500 300 3 3 0.25 0.25 µA V µA mA pF Notes: 6. Total IDD = IDDQ + IADD = FCK CPD VDDQ, solving for CPD = (IDDQ + IADD)/(FCK*VDDQ) where FCK is the input frequency, VDDQ is the power supply and CPD is the Power Dissipation Capacitance. 5 PS8689B 08/05/04 5 Page Packaging Mechanical: 52-Pin VFBGA (NF) www.DataSheet4U.com PI6CU877 PLL Clock Driver for 1.8V DDR2 Memory Ordering Information Ordering Code PI6CU877NF PI6CU877NFE Package Code NF NF Package Description 52-ball VFBGA Pb-free & Green, 52-ball VFBGA Notes: 1. Thermal characteristics can be found on the company web site at http://www.pericom.com/packaging/ Pericom Semiconductor Corporation • 1-800-435-2336 • http://www.pericom.com 11 PS8689B 08/05/04 11 Page

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