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PDF SSD1805 Data sheet ( Hoja de datos )
| Número de pieza | SSD1805 | |
| Descripción | 132 x 68 STN LCD Segment / Common Monochrome Driver | |
| Fabricantes | Solomon Systech | |
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Hay una vista previa y un enlace de descarga de SSD1805 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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SOLOMON SYSTECH
SEMICONDUCTOR TECHNICAL DATA
www.DataSheet4U.com
SSD1805
Advance Information
132 x 68 STN
LCD Segment / Common Monochrome Driver with Controller
This document contains information on a new product. Specifications and information herein are subject to change
without notice.
http://www.solomon-systech.com
SSD1805 Series Rev 1.1 P 1/52 Jun 2004
Copyright 2004 Solomon Systech Limited
1 page  
1 General Description
SSD1805 is a single-chip CMOS LCD driver with controller for dot-matrix graphic liquid crystal display system.
SSD1805 consists of 200 high-voltage driving output pins for driving maximum 132 Segments, 68 Commons /
132 Segments, 64 Commons and 1 icon-driving Common / 132 Segments, 54 Commons and 1 icon-driving
Common / 132 Segments, 32 Commons and 1 icon-driving Common. SSD1805 can also be switched among
32, 54, 64 or 68 display multiplex ratios by hardware pin selection.
SSD1805 consists of 132 x 68 bits Graphic Display Data RAM (GDDRAM). Data/Commands are sent from
common MCU through 8-bit 6800-series / 8080-series compatible Parallel Interface or 4-wires Serial
Peripheral Interface by software program selections.
www.DataSheeSt4SUD.c1om805 embeds DC-DC Converter, On-Chip Oscillator and Bias Divider to reduce the number of external
components. With the advance design, low power consumption, stable LCD operating voltage and flexible die
package layout, SSD1805 is suitable for any portable battery-driven applications requiring long operation
period with compact size.
2 FEATURES
• Power Supply: VDD = 1.8V – 3.6V
VDDIO = 1.8V – 3.6V
VCI = 1.8V – 3.6V
• LCD Driving Output Voltage: VLCD = +12.5V
• Low Current Sleep Mode
• Pin selectable 68/64/54/32 multiplex ratio configuration. Maximum display size:
o 132 columns by 68 rows
o 132 columns by 64 rows with one icon line
o 132 columns by 54 rows with one icon line
o 132 columns by 32 rows with one icon line
• 8-bit 6800-series / 8080-series Parallel Interface, 4-wires Serial Peripheral Interface
• On-Chip 132 X 68 = 8976 bits Graphic Display Data RAM
• Column Re-mapping and RAM Page scan direction control
• Vertical Scrolling by Common
• On-Chip Voltage Generator or External LCD Driving Power Supply Selectable
• Pin selectable 2X/3X/4X/5X On-Chip DC-DC Converter with internal flying capacitors.
• 64 Levels Internal Contrast Control
• Programmable LCD Driving Voltage Temperature Compensation Coefficients
• On-Chip Bias Divider with internal compensation capacitors (except VOUT)
• Programmable multiplex ratio: 1/9 to 1/68
• Programmable bias ratio: 1/4, 1/5, 1/6, 1/7, 1/8, 1/9
• Display Offset Control
• Non-Volatile Memory (OTP) for calibration
3 ORDERING INFORMATION
Ordering Part Number
SSD1805Z
SSD1805TR1
SEG
132
132
COM
64/54/32 +
1 icon or
68
64 + 1 icon
Package Form
Gold Bump Die
TAB
Reference
Figure 2 on
Page 7
Figure 20 on
page 50
Table 1 - Ordering Information
Remark
-
-
SSD1805 Series Rev 1.1 P 5/52 Jun 2004
Solomon Systech
5 Page 
6 PIN DESCRIPTION
6.1 MSTAT
This pin is the static indicator driving output. The frame signal output pin, M, should be used as the back
plane signal for the static indicator. The duration of overlapping could be programmable. See Extended
Command Table for details.
6.2 M
This pin is the frame signal input/output. In master mode, the pin supplies frame signal to slave devices while
in slave mode, the pin receives frame signal from the master device.
www.DataShee6t4.U3.comCL
This pin is the display clock input/output. In master mode with internal oscillator enabled (CLS pin pulled
high), this pin supplies display clock signal to slave devices. In slave mode or when internal oscillator is
disabled, the pin receives display clock signal from the master device or external clock source.
6.4 /DOF
This pin is display blanking control between master and slave devices. In master mode, this pin supplies
on/off signal to slave devices. In slave mode, this pin receives on/off signal from the master device.
6.5 CS 1, CS2
These pins are the chip select inputs. The chip is enabled for MCU communication only when both CS 1 is
pulled low and CS2 is pulled high.
6.6 RES
This pin is the reset signal input. Initialization of the chip is started once this pin is pulled low. Minimum pulse
width for reset sequence is 20us.
6.7 D/ C
This pin is Data/Command control pin. When the pin is pulled high, the data at D7 - D0 is treated as display
data. When the pin is pulled low, the data at D7 - D0 will be transferred to the command register.
6.8 R/W ( WR )
This pin is MCU interface input. When 6800 interface mode is selected, this pin will be used as Read/Write
(R/W ) selection input. Read mode will be carried out when this pin is pulled high and write mode when low.
When 8080 interface mode is selected, this pin is the Write ( WR ) control signal input. Data write operation is
initiated when this pin is pulled low and the chip is selected. When serial interface mode is selected, this pin
must be pulled low.
6.9 E( RD )
This pin is MCU interface input. When 6800 interface mode is selected, this pin will be used as the Enable (E)
signal. Read/write operation is initiated when this pin is pulled high and the chip is selected. When 8080
interface mode is selected, this pin is the Read ( RD ) control signal input. Data read operation is initiated
when this pin is pulled low and the chip is selected. When serial interface mode is selected, this pin must be
pulled high.
6.10 D7 - D0
These pins are the 8-bit bi-directional data bus in parallel interface mode. D7 is the MSB while D0 is the LSB.
When serial mode is selected, D7 is the serial data input (SDA) and D6 is the serial clock input (SCK).
SSD1805 Series Rev 1.1 P 11/52 Jun 2004
Solomon Systech
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SSD1805.PDF ] | |
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