PDF SSTVF16859 Data sheet ( Hoja de datos )

Número de pieza	SSTVF16859
Descripción	13-bit 1:2 SSTL_2 registered buffer
Fabricantes	NXP Semiconductors
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No Preview Available ! SSTVF16859 13-bit 1 : 2 SSTL_2 registered buffer for DDR Rev. 02 — 19 July 2005 Product data sheet 1. General description The SSTVF16859 is a 13-bit to 26-bit SSTL_2 registered driver with differential clock inputs, designed to operate between 2.3 V and 2.7 V for PC1600-PC2700 applications or between 2.5 V and 2.7 V for PC3200 applications. All inputs are compatible with the JEDEC standard for SSTL_2 with Vref normally at 0.5 × VDD, except the LVCMOS reset (RESET) input. All outputs are SSTL_2, Class II compatible, which can be used for standard stub-series applications or capacitive loads. Master reset (RESET) asynchronously resets all registers to zero. The SSTVF16859 is intended to be incorporated into standard DIMM (Dual In-Line Memory Module) designs deﬁned by JEDEC, such as DDR (Double Data Rate) SDRAM and SDRAM II Memory Modules. Different from traditional SDRAM, DDR SDRAM transfers data on both clock edges (rising and falling), thus doubling the peak bus bandwidth. A DDR DRAM rated at 133 MHz will have a burst rate of 266 MHz. The device data inputs consist of different receivers. One differential input is tied to the input pin while the other is tied to a reference input pad, which is shared by all inputs. The clock input is fully differential (CK and CK) to be compatible with DRAM devices that are installed on the DIMM. Data are registered at the crossing of CK going HIGH, and CK going LOW. However, since the control inputs to the SDRAM change at only half the data rate, the device must only change state on the positive transition of the CK signal. In order to be able to provide deﬁned outputs from the device even before a stable clock has been supplied, the device has an asynchronous input pin (RESET), which when held to the LOW state, resets all registers and all outputs to the LOW state. The device supports low-power standby operation. When RESET is LOW, the differential input receivers are disabled, and un-driven (ﬂoating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET is LOW, all registers are reset, and all outputs are forced LOW. The LVCMOS RESET input must always be held at a valid logic HIGH or LOW level. To ensure deﬁned outputs from the register before a stable clock has been supplied, RESET must be held in the LOW state during power-up. In the DDR DIMM application, RESET is speciﬁed to be completely asynchronous with respect to CK and CK. Therefore, no timing relationship can be guaranteed between the two. When entering RESET, the register will be cleared and the outputs will be driven LOW. As long as the data inputs are LOW, and the clock is stable during the time from the LOW-to-HIGH transition of RESET until the input receivers are fully enabled, the outputs will remain LOW. 1 page Philips Semiconductors SSTVF16859 13-bit 1 : 2 SSTL_2 registered buffer for DDR ball A1 SSTVF16859EC index area 123456 A B C D E F G H J K L M N P R T 002aab619 Transparent top view Fig 4. Pin conﬁguration for LFBGA96 1 A n.c. B Q12A C Q10A D Q8A E Q6A F Q4A G Q2A H Q1A J Q12B K Q10B L Q8B M Q6B N Q4B P Q2B R n.c. T n.c. 2 n.c. Q13A Q11A Q9A Q7A Q5A Q3A Q13B Q11B Q9B Q7B Q5B Q3B Q1B n.c. n.c. 3 n.c. GND GND VDDQ VDDQ VDDQ GND GND GND VDDQ VDDQ VDDQ GND GND n.c. n.c. 4 n.c. GND GND VDDQ VDDQ VDDQ GND GND VREF VDDQ VDDQ VDDQ GND GND n.c. n.c. All VDD and VDDQ are tied internally. Fig 5. Ball mapping for LFBGA96 56 n.c. n.c. n.c. n.c. n.c. n.c. D13 D12 D11 D10 D9 D8 D7 RESET n.c. CK n.c. CK n.c. n.c. D5 D6 D3 D4 D1 D2 n.c. n.c. n.c. n.c. n.c. n.c. 002aab620 9397 750 15157 Product data sheet Rev. 02 — 19 July 2005 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. 5 of 23 5 Page Philips Semiconductors SSTVF16859 13-bit 1 : 2 SSTL_2 registered buffer for DDR 11. Dynamic characteristics Table 9: Timing requirements (PC1600-PC2700) At recommended operating conditions; VDD = 2.5 V ± 0.2 V; Tamb = 0 °C to +70 °C; unless otherwise speciﬁed. See Figure 11. Symbol Parameter Conditions Min Typ Max fclock tW clock frequency pulse duration, CK, CK, HIGH or LOW -- 2.5 - 200 - tACT tINACT tsu differential inputs active time differential inputs inactive time setup time, fast slew rate setup time, slow slew rate data before CK↑, CK↓ data before CK↑, CK↓ [1] [2] - [1] [3] - [4] [6] 0.65 [5] [6] 0.75 - - - - 22 22 - - th hold time, fast slew rate hold time, slow slew rate data after CK↑, CK↓ data after CK↑, CK↓ [4] [6] 0.75 [5] [6] 0.9 - - - - [1] This parameter is not necessarily production tested. [2] Data inputs must be below a minimum time to tACT(max), after RESET is taken HIGH. [3] Data and clock inputs must be held at valid levels (not ﬂoating) a minimum time of tINACT(max), after RESET is taken LOW. [4] For data signal input slew rate ≥ 1 V/ns. [5] For data signal input slew rate ≥ 0.5 V/ns and < 1 V/ns. [6] CK, CK signals input slew rates are ≥ 1 V/ns. Unit MHz ns ns ns ns ns ns ns Table 10: Timing requirements (PC3200) At recommended operating conditions; VDD = 2.6 V ± 0.1 V; Tamb = 0 °C to +70 °C; unless otherwise speciﬁed. See Figure 11. Symbol Parameter Conditions Min Typ Max fclock tW clock frequency pulse duration, CK, CK, HIGH or LOW -- 2.5 - 210 - tACT tINACT tsu differential inputs active time differential inputs inactive time setup time, fast slew rate setup time, slow slew rate data before CK↑, CK↓ data before CK↑, CK↓ [1] [2] - [1] [3] - [4] [6] 0.65 [5] [6] 0.75 - - - - 22 22 - - th hold time, fast slew rate hold time, slow slew rate data after CK↑, CK↓ data after CK↑, CK↓ [4] [6] 0.65 [5] [6] 0.8 - - - - [1] This parameter is not necessarily production tested. [2] Data inputs must be below a minimum time to tACT(max), after RESET is taken HIGH. [3] Data and clock inputs must be held at valid levels (not ﬂoating) a minimum time of tINACT(max), after RESET is taken LOW. [4] For data signal input slew rate ≥ 1 V/ns. [5] For data signal input slew rate ≥ 0.5 V/ns and < 1 V/ns. [6] CK, CK signals input slew rates are ≥ 1 V/ns. Unit MHz ns ns ns ns ns ns ns 9397 750 15157 Product data sheet Rev. 02 — 19 July 2005 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. 11 of 23 11 Page

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