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PDF TSPC603E Data sheet ( Hoja de datos )
| Número de pieza | TSPC603E | |
| Descripción | PowerPC 603e RISC Microprocessor Family | |
| Fabricantes | Thomson | |
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TSPC603E
PowerPC 603e™ RISC MICROPROCESSOR Family
PID6-603e Specification
DESCRIPTION
The PID6-603e implementation of PC603e (after named 603e)
is a low-power implementation of reduced instruction set com-
puter (RISC) microprocessors PowerPC™ family. The 603e
implements 32-bit effective addresses, integer data types of 8,
16 and 32 bits, and floating-point data types of 32 and 64 bits.
www.DataShTeheet46U0.3ceomis a low-power 3.3-volt design and provides four soft-
ware controllable power-saving modes.
The 603e is a superscalar processor capable of issuing and
retiring as many as three instructions per clock. Instructions
can execute out of order for increased performance ; however,
the 603e makes completion appear sequential. The 603e inte-
grates five execution units and is able to execute five instruc-
tions in parallel.
The 603e provides independent on-chip, 16-Kbyte, four-way
set-associative, physically addressed caches for instructions
and data and on-chip instruction and data memory manage-
ment units (MMUs). The MMUs contain 64-entry, two-way set-
associative, data and instruction translation lookaside buffers
that provide support for demand-paged virtual memory
address translation and variable-sized block translation.
The 603e has a selectable 32 or 64-bit data bus and a 32-bit
address bus. The 603e interface protocol allows multiple mas-
ters to complete for system resources through a central exter-
nal arbiter. The 603e supports single-beat and burst data
transfers for memory accesses, and supports memory-
mapped I/O.
The 603e uses an advanced, 3.3-V CMOS process technology
and maintains full interface compatibility with TTL devices.
The 603e integrates in system testability and debugging fea-
tures through JTAG boundary-scan capability.
MAIN FEATURES
H 2.4 SPECint95, 2.1 SPECfp95 @ 100 MHz (estimated)
H Superscalar (3 instructions per clock peak).
H Dual 16KB caches.
H Selectable bus clock.
H 32-bit compatibility PowerPC implementation.
H On chip debug support.
H PD typical = 3.2 Watts (100 MHz), full operating conditions.
H Nap, doze and sleep modes for power savings.
H Branch folding.
H 64-bit data bus (32-bit data bus option).
H 4-Gbyte direct addressing range.
H Pipelined single/double precision float unit.
IEEE 754 compatible FPU.
H IEEE P 1149-1 test mode (JTAG/C0P).
H fint max = 100/120/133 MHz.
H fbus max = 66 MHz.
H Compatible CMOS input
TTL Output.
December1998
CERQUAD 240
A suffix
CERQUAD 240
Ceramic Leaded Chip Carrier
G suffix
CBGA 255
Ceramic Ball Grid Array
SCREENING / QUALITY / PACKAGING
This product is manufactured in full compliance with :
H MIL-STD-883 class B or According to TCS standards
H Upscreenings based upon TCS standards
H Full military temperature range (Tc = -55°C, Tc = +125°C)
Industrial temperature range (Tc = –40°C, Tc = +110°C)
H VCC = 3.3 V ± 5 %.
H 240 pin Cerquad or 255 pin CBGA packages
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1 page  
TSPC603E
2.2. CBGA255 package
Figure 3 (pin matrix) shows the pinout as viewed from the top of the CBGA package. The direction of the top surface view is shown by
the side profile of the CBGA package.
Pin matrix top view
01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16
www.DataSheet4U.com
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
Not to scale
Substrate Assembly
Die
VIEW
Encapsulant
Figure 3 : CBGA 255 Top view
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5 Page 
TSPC603E
B. DETAILED SPECIFICATIONS
1. SCOPE
This drawing describes the specific requirements for the microprocessor TSPC603e, in compliance with MIL-STD-883 class B or
TCS standard screening.
2. APPLICABLE DOCUMENTS
1) MIL-STD-883 : Test methods and procedures for electronics.
2) MIL-PRF-38535 appendix A : General specifications for microcircuits.
3. REQUIREMENTS
www.DataSheet4U.com
3.1. General
The microcircuits are in accordance with the applicable documents and as specified herein.
3.2. Design and construction
3.2.1. Terminal connections
Depending on the package, the terminal connections shall be is shown in Figure 2 and Figure 4 (§ A. GENERAL DESCRIPTION).
3.2.2. Lead material and finish
Lead material and finish shall be as specified in MIL-STD-1835 (see enclosed § 8)
3.2.3. Hermetic Package
The macrocircuits are packaged in 240 pin ceramic quad flat packages (see § 8.1)
The precise case outlines are described at the end of the specification (§ 8.1) and into MIL-STD-1835.
3.3. Absolute maximum ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond
those listed may affect device reliability or cause permanent damage to the device.
Table 5 : Absolute maximum rating for the 603e
Parameter
Symbol
Min
Max
Unit
Core supply voltage
PLL supply voltage
I/O supply voltage
Input voltage
Storage temperature range
VDD -0.3
4.0
AVDD
-0.3
4.0
OVDD
-0.3
4.0
Vin -0.3 5.5
Tstg -55 +150
V
V
V
V
°C
Note 1 : Functional operating conditions are given in AC and DC electrical specifications. Stresses beyond the absolute maximums listed may affect
device reliability or cause permanent damage to the device.
Note 2 : Caution : Input voltage must not be greater than the OVDD supply voltage by more than 2.5 V at all times including during power-on reset.
Note 3 : Caution : OVDD voltage must not be greater than AVDD supply voltage by more than 2.5 V at all times including during power-on reset.
Note 4 : Caution : AVDD voltage must not be greater than OVDD supply voltage by more than 0.4 V at all times including during power-on reset.
3.4. Recommended operating conditions
These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not garanteed.
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