PDF MT28C6428P20 Data sheet ( Hoja de datos )

Número de pieza	MT28C6428P20
Descripción	(MT28C6428P18 / MT28C6428P20) FLASH AND SRAM COMBO MEMORY
Fabricantes	Micron Technology
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ADVANCE‡ 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY FLASH AND SRAM COMBO MEMORY MT28C6428P20 MT28C6428P18 Low Voltage, Extended Temperature 0.18µm Process Technology FEATURES • Flexible dual-bank architecture • Support for true concurrent operations with no www.DataSheetl4aUt.econmcy: Read bank b during program bank a and vice versa Read bank b during erase bank a and vice versa • Organization: 4,096K x 16 (Flash) 512K x 16 (SRAM) • Basic configuration: Flash Bank a (16Mb Flash for data storage) – Eight 4K-word parameter blocks – Thirty-one 32K-word blocks Bank b (48Mb Flash for program storage) – Ninety-six 32K-word main blocks SRAM 8Mb SRAM for data storage – 512K-words • F_VCC, VCCQ, F_VPP, S_VCC voltages MT28C6428P20 1.80V (MIN)/2.20V (MAX) F_VCC read voltage 1.80V (MIN)/2.20V (MAX) S_VCC read voltage 1.80V (MIN)/2.20V (MAX) VCCQ MT28C6428P18 1.70V (MIN)/1.90V (MAX) F_VCC read voltage 1.70V (MIN)/1.90V (MAX) S_VCC read voltage 1.70V (MIN)/1.90V (MAX) VCCQ MT28C6428P20/P18 1.80V (TYP) F_VPP (in-system PROGRAM/ERASE) 1.0V (MIN) S_VCC (SRAM data retention) 12V ±5% (HV) F_VPP (in-house programming and accelerated programming algorithm [APA] activation) • Asynchronous access time Flash access time: 80ns @ 1.80V F_VCC SRAM access time: 80ns @ 1.80V S_VCC • Page Mode read access Interpage read access: 80ns @ 1.80V F_VCC Intrapage read access: 30ns @ 1.80V F_VCC • Low power consumption • Enhanced suspend options ERASE-SUSPEND-to-READ within same bank PROGRAM-SUSPEND-to-READ within same bank ERASE-SUSPEND-to-PROGRAM within same bank • Read/Write SRAM during program/erase of Flash BALL ASSIGNMENT 67-Ball FBGA (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 A NC NC A20 A11 A15 A14 A13 A12 F_VSS VccQ NC NC B A16 A8 A10 A9 DQ15 S_WE# DQ14 DQ7 C F_WE# NC A21 DQ13 DQ6 DQ4 DQ5 D VSS F_RP# DQ12 S_CE2 S_VCC F_VCC E F_WP# F_VPP A19 DQ11 DQ10 DQ2 DQ3 F S_LB# S_UB# S_OE# DQ9 DQ8 DQ0 DQ1 G A18 A17 A7 A6 A3 A2 A1 S_CE1# H NC NC F_VCC A5 A4 A0 F_CE# F_VSS F_OE# NC NC NC Top View (Ball Down) • Dual 64-bit chip protection registers for security purposes • PROGRAM/ERASE cycles 100,000 WRITE/ERASE cycles per block • Cross-compatible command set support Extended command set Common flash interface (CFI) compliant OPTIONS • Timing 80ns 85ns • Boot Block Configuration Top Bottom • Operating Voltage Range F_VCC = 1.70V–1.90V F_VCC = 1.80V–2.20V • Operating Temperature Range Commercial (0oC to +70oC) Extended (-40oC to +85oC) • Package 67-ball FBGA (8 x 8 grid) MARKING -80 -85 T B 18 20 None ET FM Part Number Example: MT28C6428P20FM-80 BET 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02 1 ©2002, Micron Technology, Inc. ‡PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS. 1 page ADVANCE 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY BALL DESCRIPTIONS 67-BALL FBGA NUMBERS H6, G9, G8, G7, H5, H4, G6, G5, B4, B6, B5, A4, A8, A7, A6, A5, B3, G4, G3, E5, A3, C5 www.DataSheet4U.coHm7 SYMBOL A0–A21 F_CE# TYPE Input Input H9 F_OE# Input C3 F_WE# Input D4 F_RP# Input E3 F_WP# Input G10 S_CE1# Input D8 S_CE2 Input F5 S_OE# Input B8 S_WE# Input F3 S_LB# Input F4 S_UB# Input F9, F10, E9, DQ0–DQ15 Input/ E10, C9, C10, Output C8, B10, F8, F7, E8, E6, D7, C7, B9, B7 DESCRIPTION Address Inputs: Inputs for the addresses during READ and WRITE operations. Addresses are internally latched during READ and WRITE cycles. Flash: A0–A21; SRAM: A0–A18. Flash Chip Enable: Activates the device when LOW. When CE# is HIGH, the device is disabled and goes into standby power mode. Flash Output Enable: Enables Flash output buffers when LOW. When F_OE# is HIGH, the output buffers are disabled. Flash Write Enable: Determines if a given cycle is a Flash WRITE cycle. F_WE# is active LOW. Reset. When F_RP# is a logic LOW, the device is in reset, which drives the outputs to High-Z and resets the WSM. When F_RP# is a logic HIGH, the device is in standard operation. When F_RP# transitions from logic LOW to logic HIGH, the device resets all blocks to locked and defaults to the read array mode. Flash Write Protect. Controls the lock down function of the flexible locking feature. SRAM Chip Enable1: Activates the SRAM when it is LOW. HIGH level deselects the SRAM and reduces the power consumption to standby levels. SRAM Chip Enable2: Activates the SRAM when it is HIGH. LOW level deselects the SRAM and reduces the power consumption to standby levels. SRAM Output Enable: Enables SRAM output buffers when LOW. When S_OE# is HIGH, the output buffers are disabled. SRAM Write Enable: Determines if a given cycle is an SRAM WRITE cycle. S_WE# is active LOW. SRAM Lower Byte: When LOW, it selects the SRAM address lower byte (DQ0–DQ7). SRAM Upper Byte: When LOW, it selects the SRAM address upper byte (DQ8–DQ15). Data Inputs/Outputs: Input array data on the second CE# and WE# cycle during PROGRAM command. Input commands to the command user interface when CE# and WE# are active. Output data when CE# and OE# are active. (continued on next page) 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. 5 Page ADVANCE 4 MEG x 16 ASYNCHRONOUS/PAGE FLASH 512K x 16 SRAM COMBO MEMORY Register data is updated and latched on the falling edge of F_OE# or F_CE#, whichever occurs last. The latest falling edge of either of these two signals up- dates the latch within a given READ cycle. Latching the data prevents errors from occurring if the register input changes during a status register read. The status register provides the internal state of the WSM to the external microprocessor. During periods when the WSM is active, the status register can be polled to determine the WSM status. Table 8 defines the sta- tus register bits. www.DataSheet4AUf.ctoemr monitoring the status register during a PROGRAM/ERASE operation, the data appearing on DQ0–DQ7 remains as status register data until a new command is issued to the CSM. To return the device to other modes of operation, a new command must be issued to the CSM. COMMAND STATE MACHINE OPERATIONS The CSM decodes instructions for the commands listed in Table 3. The 8-bit command code is input to the device on DQ0–DQ7 (see Table 4 for command definitions). During a PROGRAM or ERASE cycle, the CSM informs the WSM that a PROGRAM or ERASE cycle has been requested. During a PROGRAM cycle, the WSM controls the program sequences and the CSM responds to a PRO- GRAM SUSPEND command only. During an ERASE cycle, the CSM responds to an ERASE SUSPEND command only. When the WSM has completed its task, the WSMS bit (SR7) is set to a logic HIGH level and the CSM responds to the full command set. The CSM stays in the current command state until the microprocessor issues another command. The WSM successfully initiates an ERASE or PRO- GRAM operation only when F_VPP is within its correct voltage range. Table 4 Command Definitions COMMAND FIRST BUS CYCLE OPERATION ADDRESS1 DATA READ ARRAY WRITE WA FFh READ PROTECTION CONFIGURATION REGISTER WRITE IA 90h READ STATUS REGISTER WRITE BA 70h CLEAR STATUS REGISTER WRITE BA 50h READ QUERY WRITE QA 98h BLOCK ERASE SETUP WRITE BA 20h PROGRAM SETUP WRITE WA 40h ACCELERATED PROGRAMMING ALGORITHM (APA) WRITE WA 10h PROGRAM/ERASE SUSPEND WRITE BA B0h PROGRAM/ERASE RESUME – ERASE CONFIRM WRITE BA D0h LOCK BLOCK WRITE BA 60h UNLOCK BLOCK WRITE BA 60h LOCK DOWN BLOCK WRITE BA 60h CHECK BLOCK ERASE WRITE BA 20h PROTECTION REGISTER PROGRAM WRITE PA C0h PROTECTION REGISTER LOCK WRITE LPA C0h ENABLE/DISABLE DEEP POWER-DOWN WRITE DPW 60h SECOND BUS CYCLE OPERATION ADDRESS1 DATA1 READ READ IA X ID SRD READ WRITE WRITE WRITE QA BA WA WA QD D0h WD WD WRITE WRITE WRITE WRITE WRITE WRITE WRITE BA BA BA BA PA LPA DPW 01h D0h 2Fh D1h PD FFFDh 03h NOTE: 1. BA: Address within the block DPW:BBCFh = Disable deep power-down BBDFh = Enable deep power-down IA: Identification code address ID: Identification code data LPA: Lock protection register address PA: Protection register address PD: Data to be written at location PA QA: Query code address QD: Query code data SRD: Data read from the status register WA: Word address of memory location to be written, or read WD: Data to be written at the location WA X: “Don’t Care” 4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. 11 Page

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