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PDF ASM5I2308A Data sheet ( Hoja de datos )
| Número de pieza | ASM5I2308A | |
| Descripción | 3.3 V Zero Delay Buffer | |
| Fabricantes | Alliance Semiconductor | |
| Logotipo |  |
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September 2005
ASM5P2308A
rev 1.4
3.3V Zero-Delay Buffer
General Features
allows the input clock to be directly applied to the outputs
• Zero input - output propagation delay, adjustable by
for chip and system testing purposes.
capacitive load on FBK input.
• Multiple configurations - Refer “ASM5P2308A
Configurations “ Table.
www.DataSheet•4U.coInmput frequency range: 15MHz to 133MHz
• Multiple low-skew outputs.
Multiple ASM5P2308A devices can accept the same input
clock and distribute it. In this case the skew between the
outputs of the two devices is guaranteed to be less than
700pS.
• Output-output skew less than 200pS.
• Device-device skew less than 700pS.
• Two banks of four outputs, tri-stateable by two select
inputs.
• Less than 200pS cycle-to-cycle jitter
(-1, -1H,-2, -3, -4, -5H).
• Available in 16 pin SOIC and TSSOP packages.
• 3.3V operation.
The ASM5P2308A is available in five different
configurations(Refer “ASM5P2308A Configurations” Table).
The ASM5P2308A-1 is the base part, where the output
frequencies equal the reference if there is no counter in the
feedback path. The ASM5P2308A-1H is the high-drive
version of the -1 and the rise and fall times on this device
are much faster.
• Advanced 0.35µ CMOS technology.
• Industrial temperature available.
Functional Description
The ASM5P2308A-2 allows the user to obtain 2X and 1X
frequencies on each output bank. The exact configuration
and output frequencies depends on which output drives the
ASM5P2308A is a versatile, 3.3V zero-delay buffer
designed to distribute high-speed clocks. It is available in a
feedback pin. The ASM5P2308A-3 allows the user to
obtain 4X and 2X frequencies on the outputs.
16 pin package. The part has an on-chip PLL which locks
to an input clock presented on the REF pin. The PLL
feedback is required to be driven to FBK pin, and can be
The ASM5P2308A-4 enables the user to obtain 2X clocks
on all outputs.
obtained from one of the outputs. The input-to-output
propagation delay is guaranteed to be less than 250pS,
and the output-to-output skew is guaranteed to be less than
200pS.
The ASM5P2308A-5H is a high-drive version with REF/2
on both banks. Thus, the part is extremely versatile, and
can be used in a variety of applications.
The ASM5P2308A has two banks of four outputs each,
which can be controlled by the select inputs as shown in
the Select Input Decoding Table. The select input also
Alliance Semiconductor
2575 Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com
Notice: The information in this document is subject to change without notice.
1 page  
September 2005
rev 1.4
ASM5P2308A
Absolute Maximum Ratings
Parameter
Supply Voltage to Ground Potential
DC Input Voltage (Except REF)
DC Input Voltage (REF)
Storage Temperature
Max. Soldering Temperature (10 sec)
www.DataSheet4U.com
Junction Temperature
Static Discharge Voltage (As per JEDEC STD22- A114-B)
Min
-0.5
-0.5
-0.5
-65
Max
+7.0
VDD + 0.5
7
+150
260
150
2000
Unit
V
V
V
°C
°C
°C
V
Note: These are stress ratings only and functional usage is not implied. Exposure to absolute maximum ratings for prolonged periods can affect device
reliability.
Operating Conditions for ASM5P2308A Commercial Temperature Devices
Parameter
Description
Min
VDD Supply Voltage
TA Operating Temperature (Ambient Temperature)
CL Load Capacitance, below 100MHz
CL Load Capacitance, from 100MHz to 133MHz
CIN Input Capacitance6
3.0
0
Note:
6. Applies to both Ref Clock and FBK.
Electrical Characteristics for ASM5P2308A Commercial Temperature Devices
Max
3.6
70
30
15
7
Unit
V
°C
pF
pF
pF
Parameter
Description
Test Conditions
VIL Input LOW Voltage
VIH Input HIGH Voltage
IIL Input LOW Current
VIN = 0V
IIH Input HIGH Current
VIN = VDD
VOL Output LOW Voltage 7 IOL = 8mA (-1, -2, -3, -4)
IOH = 12mA (-1H, -5H)
VOH Output HIGH Voltage 7 IOL = -8mA (-1, -2, -3, -4)
IOH = -12mA (-1H, -5H)
Unloaded outputs 100MHz REF (-2,-3,-4)
IDD
Supply Current8
Select inputs at VDD or GND
(-1H,-5H)
Unloaded outputs, 66MHz REF (-1, -2, -3, -4)
Unloaded outputs, 33MHz REF (-1, -2, -3, -4)
Note:
7. Parameter is guaranteed by design and characterization. Not 100% tested in production.
8. Supply Currents are measured for PLL-Bypass Mode (S2=1, S1=0)
Min Max Unit
0.8 V
2.0 V
50.0 µA
100.0
µA
0.4 V
2.4 V
49
60
mA
34
18
3.3V Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
5 of 18
5 Page 
September 2005
rev 1.4
Package Information
16-lead (150 Mil) Molded SOIC Package
www.DataSheet4U.com
8 1 PIN 1 ID
EH
9 16
D
e
B
Seating Plane
A2
A
0.004
A1
θ
ASM5P2308A
h
C
L
Symbol
A
A1
A2
B
C
D
E
e
H
h
L
θ
Dimensions
Inches
Millimeters
Min Max Min Max
0.053
0.069
1.35
1.75
0.004
0.010
0.10
0.25
0.049
0.059
1.25
1.50
0.013
0.022
0.33
0.53
0.008
0.012
0.19
0.27
0.386
0.394
9.80
10.01
0.150
0.157
3.80
4.00
0.050 BSC
1.27 BSC
0.228
0.244
5.80
6.20
0.010
0.016
0.25
0.41
0.016
0.035
0.40
0.89
0° 8° 0° 8°
3.3V Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
11 of 18
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