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PDF CYV15G0404DXB Data sheet ( Hoja de datos )
| Número de pieza | CYV15G0404DXB | |
| Descripción | Independent Clock Quad HOTLink IIBT Transceiver with Reclocker | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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PRELIMINARY
CYV15G0404DXB
Independent Clock Quad HOTLink II™ Transceiver
with Reclocker
Features
• Quad channel transceiver for 195- to 1500-MBaud serial
signaling rate
— Aggregate throughput of up to 12 Gbits/second
• Second-generation HOTLink® technology
• Compliant to multiple standards
www.DataSheet4U—.coSCmMhaPnTnEe-l2, 9E2SMC,OSNMaPnTdE-G2i5g9aMb,itDEVtBhe-ArnSeI,t
Fibre
(IEEE802.3z)
— 10 bit uncoded data or 8B/10B coded data
• Truly independent channels
— Each channel can perform reclocker function
— Each channel can operate at a different signaling
rate
— Each channel can transport a different data format
• Internal phase-locked loops (PLLs) with no external
PLL components
• Selectable differential PECL-compatible serial inputs
per channel
— Internal DC-restoration
• Redundant differential PECL-compatible serial outputs
per channel
— No external bias resistors required
— Signaling-rate controlled edge-rates
— Source matched for 50Ω transmission lines
• MultiFrame™ Receive Framer provides alignment
options
— Comma or Full K28.5 detect
— Single or Multi-byte Framer for byte alignment
— Low-latency option
• Selectable input/output clocking options
• Synchronous LVTTL parallel interface
• JTAG boundary scan
• Built-In Self-Test (BIST) for at-speed link testing
• Per-channel Link Quality Indicator
— Analog signal detect
— Digital signal detect
• Low-power 3W @ 3.3V typical
• Single 3.3V supply
• 256-ball thermally enhanced BGA
• 0.25µ BiCMOS technology
• JTAG device ID ‘0C811069’x
Functional Description
The CYV15G0404DXB Independent Clock Quad HOTLink II™
Transceiver is a point-to-point or point-to-multipoint communi-
cations building block enabling transfer of data over a variety
of high-speed serial links including SMPTE 292, SMPTE 259
and DVB-ASI video applications. The signaling rate can be
anywhere in the range of 195 to 1500 MBaud per serial link.
Each channel operates independently with its own reference
clock allowing different rates. Each transmit channel accepts
parallel characters in an Input Register, encodes each
character for transport, and then converts it to serial data.
Each receive channel accepts serial data and converts it to
parallel data, decodes the data into characters, and presents
these characters to an Output Register. The received serial
data can also be reclocked and retransmitted through the
serial outputs. Figure 1 illustrates typical connections between
independent video co-processors and corresponding
CYV15G0404DXB chips.
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Independent
Channel
CYV15G0404DXB
Reclocker
Serial Links
Serial Links
Serial Links
Independent
Channel
CYV15G0404DXB
Reclocker
Serial Links
Cable
Connections
Figure 1. HOTLink II™ System Connections
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Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-02097 Rev. **
Revised June 04, 2004
1 page  
PRELIMINARY
Device Configuration and Control Block Diagram
WREN
ADDR[3:0]
DATA[7:0]
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Device Configuration
and Control Interface
RFMODE[A..D][1:0]
RFEN[A..D]
FRAMCHAR[A..D]
DECMODE[A..D]
RXBIST[A..D]
RXCKSEL[A..D]
DECBYP[A..D]
RXRATE[A..D]
SDASEL[A..D][1:0]
RXPLLPD[A..D]
TXRATE[A..D]
TXCLKSEL[A..D]
PABRST[A..D]
TXBIST[A..D]
OE[A..D][2..1]
ENCBYP[A..D]
GLEN[11..0]
FLEN[2..0]
CYV15G0404DXB
= Internal Signal
Document #: 38-02097 Rev. **
Page 5 of 43
5 Page 
PRELIMINARY
CYV15G0404DXB
Pin Definitions (continued)
CYV15G0404DXB Quad HOTLink II Transceiver
Name
I/O Characteristics Signal Description
LFIA
LVTTL Output,
Link Fault Indication Output. LFIx is an output status indicator signal. LFIx is the
LFIB
asynchronous
logical OR of five internal conditions. LFIx is asserted LOW when any of the
LFIC
following conditions is true:
LFID
• Received serial data rate outside expected range
• Analog amplitude below expected levels
• Transition density lower than expected
• Receive channel disabled
• ULCx is LOW
• Absence of REFCLKx±.
www.DataSheet4UD.ceovmice Configuration and Control Bus Signals
WREN
LVTTL input,
asynchronous,
internal pull-up
Control Write Enable. The WREN input writes the values of the DATA[7:0] bus
into the latch specified by the address location on the ADDR[3:0] bus.[5]
ADDR[3:0]
LVTTL input
asynchronous,
internal pull-up
Control Addressing Bus. The ADDR[3:0] bus is the input address bus used to
configure the device. The WREN input writes the values of the DATA[7:0] bus into
the latch specified by the address location on the ADDR[3:0] bus.[5] Table 9 lists
the configuration latches within the device, and the initialization value of the
latches upon the assertion of RESET. Table 10 shows how the latches are
mapped in the device.
DATA[7:0]
LVTTL input
asynchronous,
internal pull-up
Control Data Bus. The DATA[7:0] bus is the input data bus used to configure the
device. The WREN input writes the values of the DATA[7:0] bus into the latch
specified by address location on the ADDR[3:0] bus.[5 ] Table 9 lists the configu-
ration latches within the device, and the initialization value of the latches upon the
assertion of RESET. Table 10 shows how the latches are mapped in the device.
Internal Device Configuration Latches
RFMODE[A..D][1:0] Internal Latch[6]
FRAMCHAR[A..D] Internal Latch[6]
DECMODE[A..D] Internal Latch[6]
DECBYP[A..D]
Internal Latch[6]
RXCKSEL[A..D] Internal Latch[6]
RXRATE[A..D]
Internal Latch[6]
SDASEL[A..D][1:0] Internal Latch[6]
ENCBYP[A..D]
Internal Latch[6]
TXCKSEL[A..D]
Internal Latch[6]
TXRATE[A..D]
Internal Latch[6]
RFEN[A..D]
Internal Latch[6]
RXPLLPD[A..D]
Internal Latch[6]
RXBIST[A..D]
Internal Latch[6]
TXBIST[A..D]
Internal Latch[6]
OE2[A..D]
Internal Latch[6]
OE1[A..D]
Internal Latch[6]
PABRST[A..D]
Internal Latch[6]
GLEN[11..0]
Internal Latch[6]
FGLEN[2..0]
Internal Latch[6]
Reframe Mode Select.
Framing Character Select.
Receiver Decoder Mode Select.
Receiver Decoder Bypass.
Receive Clock Select.
Receive Clock Rate Select.
Signal Detect Amplitude Select.
Transmit Encoder Bypassed.
Transmit Clock Select.
Transmit PLL Clock Rate Select.
Reframe Enable.
Receive Channel Power Control.
Receive Bist Disabled.
Transmit Bist Disabled.
Differential Serial Output Driver 2 Enable.
Differential Serial Output Driver 1 Enable.
Transmit Clock Phase Alignment Buffer Reset.
Global Latch Enable.
Force Global Latch Enable.
Factory Test Modes
Note:
6. See Device Configuration and Control Interface for detailed information on the internal latches.
Document #: 38-02097 Rev. **
Page 11 of 43
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