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PDF CYV15G0403TB Data sheet ( Hoja de datos )
| Número de pieza | CYV15G0403TB | |
| Descripción | Independent Clock Quad HOTLink IIBT Serializer | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CYV15G0403TB
Independent Clock Quad HOTLink II™
Serializer
Features
Functional Description
• Second-generation HOTLink® technology
• Compliant to SMPTE 292M and SMPTE 259M video
standards
• Quad channel video serializer
— 195- to 1500-Mbps serial data signaling rate
www.DataSheet4U—.coSmimultaneous operation at different signaling rates
• Supports half-rate and full-rate clocking
• Internal phase-locked loops (PLLs) with no external PLL
components
• Redundant differential PECL-compatible serial outputs per
channel
— No external bias resistors required
— Signaling-rate controlled edge-rates
— Internal source termination
• Synchronous LVTTL parallel interface
• JTAG boundary scan
• Built-In Self-Test (BIST) for at-speed link testing
• Low-power 2W @ 3.3V typical
• Single 3.3V supply
• Thermally enhanced BGA
• Pb-Free package option available
• 0.25μ BiCMOS technology
The CYV15G0403TB Independent Clock Quad HOTLink II™
Serializer is a point-to-point or point-to-multipoint communica-
tions building block enabling transfer of data over a variety of
high-speed serial links including SMPTE 292M and SMPTE
259M video applications. It supports signaling rates in the
range of 195 to 1500 Mbps per serial link. All four channels are
independent and can simultaneously operate at different
rates. Each channel accepts 10-bit parallel characters in an
Input Register and converts them to serial data. Figure 1 illus-
trates typical connections between independent video
co-processors and corresponding CYV15G0403TB Serializer
and CYV15G0404RB Reclocking Deserializer chips.
The CYV15G0403TB satisfies the SMPTE-259M and
SMPTE-292M compliance as per SMPTE EG34-1999 Patho-
logical Test Requirements.
As a second-generation HOTLink device, the
CYV15G0403TB extends the HOTLink family with enhanced
levels of integration and faster data rates, while maintaining
serial-link compatibility (data and BIST) with other HOTLink
devices. Each channel of the CYV15G0403TB Quad HOTLink
II device independently accepts scrambled 10-bit transmission
characters. These characters are serialized and output from
dual Positive ECL (PECL) compatible differential trans-
mission-line drivers at a bit-rate of either 10- or 20-times the
input reference clock for that channel.
Each channel contains an independent BIST pattern
generator. This BIST hardware allows at-speed testing of the
high-speed serial data paths in each transmit section of this
device, each receive section of a connected HOTLink II
device, and across the interconnecting links.
Figure 1. HOTLink II™ System Connections
Reclocked
Outputs
10
10
10
Independent
Channel
CYV15G0403TB
10 Serializer
Serial Links
Independent
Channel
CYV15G0404RB
Reclocking Deserializer
10
10
10
10
Reclocked
Outputs
Cypress Semiconductor Corporation
Document #: 38-02104 Rev. *C
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Revised May 2, 2007
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CYV15G0403TB
Pin Configuration (Top View)[1]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
A
NC OUT NC
C1–
B
VCC
OUT
C1+
VCC
C
TDI TMS VCC
www.DataSheet4UD.comTCLK RESET VCC
E
VCC VCC VCC
OUT
C2–
OUT
C2+
VCC
VCC
VCC
VCC
VCC
VCC
VCC
NC
OUT GND GND OUT GND OUT GND GND OUT
D1– D2– A1– A2–
VCC
VCC
OUT GND
D1+
NC
OUT
D2+
NC
OUT GND NC
A1+
OUT
A2+
VCC
NC
NC GND NC
NC
DATA DATA GND
[3] [1]
NC
SPD
SELD
VCC
VCC
SPD GND GND
SELC
DATA
[4]
DATA
[2]
DATA
[0]
GND
GND
NC
VCC
VCC
OUT
B1–
VCC
OUT
B2–
NC OUT NC OUT
B1+ B2+
NC TRST GND TDO
NC NC SCAN TMEN3
EN2
VCC VCC VCC VCC
F
NC NC TX NC
DC[0]
G
TX WREN TX
TX
DC[7]
DC[4] DC[1]
H
GND GND GND GND
NC NC TX NC
CLKOB
SPD NC SPD NC
SELB
SELA
GND GND GND GND
J
TX TX TX TX
DC[9] DC[5] DC[2] DC[3]
K
NC REF TX
TX
CLKC– DC[8] CLKC
L
NC REF NC TX
CLKC+
DC[6]
M
NC NC NC TX
ERRC
N
GND GND GND GND
NC NC NC NC
NC NC NC NC
NC NC NC TX
DB[6]
REF REF TX
TX
CLKB+ CLKB– ERRB CLKB
GND GND GND GND
P
NC NC NC NC
R
NC TX NC NC
CLKOC
T
VCC VCC VCC VCC
TX TX TX TX
DB[5] DB[4] DB[3] DB[2]
TX TX TX TX
DB[1] DB[0] DB[9] DB[7]
VCC VCC VCC VCC
U
TX TX TX TX
DD[0] DD[1] DD[2] DD[9]
VCC
NC
NC
GND TX ADDR REF TX GND TX
TX
DA[9] [0] CLKD– DA[1]
DA[4] DA[8]
VCC
NC TX NC
DB[8]
NC
V
TX TX TX NC
DD[3] DD[4] DD[8]
VCC
NC
NC
GND
NC
ADDR REF TX GND TX
TX
[2] CLKD+ CLKOA
DA[3] DA[7]
VCC
NC
NC
NC
NC
W
TX TX NC
DD[5] DD[7]
NC
VCC
NC
NC
GND ADDR ADDR
[3] [1]
NC
TX GND TX
TX
ERRA
DA[2] DA[6]
VCC
NC REF NC
CLKA+
NC
Y
TX TX NC
DD[6] CLKD
NC
VCC
NC
NC
GND TX
NC
CLKOD
TX
CLKA
NC
GND TX
TX
DA[0] DA[5]
VCC
TX REF
ERRD CLKA–
NC
NC
Note
1. NC = Do not connect.
Document #: 38-02104 Rev. *C
Page 5 of 21
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CYV15G0403TB
0, 1, 3, 4, 6, 7, 9, and 10) are the static control latches. The
third row of latches for each channel (address numbers 2, 5,
8, and 11) are the dynamic control latches that are associated
with enabling dynamic functions within the device.
Latch Bank 14 is also useful for those users that do not need
the latch-based programmable feature of the device. This
latch bank could be used in those applications that do not need
to modify the default value of the static latch banks, and that
can afford a global (i.e., not independent) control of the
dynamic signals. In this case, this feature becomes available
when ADDR[3:0] is left unchanged with a value of “1110” and
WREN is left asserted. The signals present in DATA[4:0] effec-
tively become global control pins, and for the latch banks 2, 5,
8 and 11.
Static Latch Values
There are some latches in the table that have a static value
(i.e. 1, 0, or X). The latches that have a ‘1’ or ‘0’ must be
configured with their corresponding value each time that their
associated latch bank is configured. The latches that have an
‘X’ are don’t cares and can be configured with any value.
www.DataSheetT4aUb.cleom2. Device Configuration and Control Latch Descriptions
Name
Signal Description
TXCKSELA
TXCKSELB
TXCKSELC
TXCKSELD
Transmit Clock Select. The initialization value of the TXCKSELx latch = 1. TXCKSELx selects the clock
source used to write data into the Transmit Input Register. When TXCKSELx = 1, the associated input
register TXDx[9:0] is clocked by REFCLKx↑. In this mode, the phase alignment buffer in the transmit path
is bypassed. When TXCKSELx = 0, the associated TXCLKx↑ is used to clock in the input register
TXDx[9:0].
TXRATEA
TXRATEB
TXRATEC
TXRATED
Transmit PLL Clock Rate Select. The initialization value of the TXRATEx latch = 0. TXRATEx is used
to select the clock multiplier for the Transmit PLL. When TXRATEx = 0, each transmit PLL multiples the
associated REFCLKx± input by 10 to generate the serial bit-rate clock. When TXRATEx = 0, the
TXCLKOx output clocks are full-rate clocks and follow the frequency and duty cycle of the associated
REFCLKx± input. When TXRATEx = 1, each Transmit PLL multiplies the associated REFCLKx± input by
20 to generate the serial bit-rate clock. When TXRATEx = 1, the TXCLKOx output clocks are twice the
frequency rate of the REFCLKx± input. When TXCLKSELx = 1 and TXRATEx = 1, the Transmit Data
Inputs are captured using both the rising and falling edges of REFCLKx. TXRATEx = 1 and SPDSELx =
LOW, is an invalid state and this combination is reserved.
TXBISTA
TXBISTB
TXBISTC
TXBISTD
Transmit Bist Disabled. The initialization value of the TXBISTx latch = 1. TXBISTx selects if the transmit
BIST is disabled or enabled. When TXBISTx = 1, the transmit BIST function is disabled. When
TXBISTx = 0, the transmit BIST function is enabled.
OE2A
OE2B
OE2C
OE2D
Secondary Differential Serial Data Output Driver Enable. The initialization value of the OE2x latch =
0. OE2x selects if the OUT2x± secondary differential output drivers are enabled or disabled. When OE2x
= 1, the associated serial data output driver is enabled allowing data to be transmitted from the transmit
shifter. When OE2x = 0, the associated serial data output driver is disabled. When a driver is disabled via
the configuration interface, it is internally powered down to reduce device power. If both serial drivers for
a channel are in this disabled state, the associated internal logic for that channel is also powered down.
A device reset (RESET sampled LOW) disables all output drivers.
OE1A
OE1B
OE1C
OE1D
Primary Differential Serial Data Output Driver Enable. The initialization value of the OE1x latch = 0.
OE1x selects if the OUT1x± primary differential output drivers are enabled or disabled. When OE1x = 1,
the associated serial data output driver is enabled allowing data to be transmitted from the transmit shifter.
When OE1x = 0, the associated serial data output driver is disabled. When a driver is disabled via the
configuration interface, it is internally powered down to reduce device power. If both serial drivers for a
channel are in this disabled state, the associated internal logic for that channel is also powered down.
A device reset (RESET sampled LOW) disables all output drivers.
PABRSTA
PABRSTB
PABRSTC
PABRSTD
Transmit Clock Phase Alignment Buffer Reset. The initialization value of the PABRSTx latch = 1. The
PABRSTx is used to re-center the Transmit Phase Align Buffer. When the configuration latch PABRSTx
is written as a 0, the phase of the TXCLKx input clock relative to its associated REFCLKx+/- is initialized.
PABRST is an asynchronous input, but is sampled by each TXCLKx↑ to synchronize it to the internal
clock domain. PABRSTx is a self clearing latch. This eliminates the requirement of writing a 1 to complete
the initialization of the Phase Alignment Buffer.
GLEN[11..0]
Global Enable. The initialization value of the GLENx latch = 1. The GLENx is used to reconfigure several
channels simultaneously in applications where several channels may have the same configuration. When
GLENx = 1 for a given address, that address is allowed to participate in a global configuration. When
GLENx = 0 for a given address, that address is disabled from participating in a global configuration.
FGLEN[2..0]
Force Global Enable. The initialization value of the FGLENx latch is NA. The FGLENx latch forces a
GLobal ENable no matter what the setting is on the GLENx latch. If FGLENx = 1 for the associated Global
channel, FGLEN forces the global update of the target latch banks.
Document #: 38-02104 Rev. *C
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| PDF Descargar | [ Datasheet CYV15G0403TB.PDF ] | |
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