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PDF CYV15G0402DXB Data sheet ( Hoja de datos )
| Número de pieza | CYV15G0402DXB | |
| Descripción | Quad HOTLink IIBT SERDES | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CYP15G0402DXB
CYV15G0402DXB
Quad HOTLink II™ SERDES
Features
• Second-generation HOTLink® technology
• Compliant to multiple standards
— Fibre Channel, Gigabit Ethernet (IEEE802.3z), ES-
CON® and DVB-ASI
— CYV15G0402DXB compliant to SMPTE 259M and
www.DataSheet4U.coSmMPTE 292M
• Quad-channel transceiver operates from 195 to 1500
Mbps serial data rate
— Aggregate throughput of 12 Gbps
• 10-bit unencoded data transport
• Selectable parity check/generate
• Four independent 10-bit channels with separate Clock
and Data Recovery for each channel
• Selectable input clocking options
• MultiFrame™ Receive Framer
— Comma or full K28.5 detect
— Single or Multi-Byte framer for byte alignment
— Low-latency option
• Synchronous LVTTL parallel interface
• Internal phase-locked loops (PLLs) with no external
PLL components
• Optional Phase Align Buffer in Transmit Path
• Differential PECL-compatible serial inputs
• Differential PECL-compatible serial outputs
— Source matched for 50Ω transmission lines
— No external resistors required
— Signaling rate controlled edge rates
• Compatible with
— Fiber-optic modules
— Copper cables
— Circuit board traces
• JTAG boundary scan
• Built-In Self-Test (BIST) for at-speed link testing
• Per-channel Link Quality Indicator
— Analog signal detect
— Digital signal detect
• Low-power 2.5W @3.3V typical
• Single 3.3V supply
• 256-ball thermally enhanced BGA
• Pb-Free package option available
• 0.25µ BiCMOS technology
Functional Description
The CYP(V)15G0402DXB[1] Quad HOTLink II™ SERDES is a
point-to-point communications building block allowing the
transfer of preencoded data over high-speed serial links
(optical fiber, balanced, and unbalanced copper transmission
lines) at signaling speeds ranging from 195 to 1500 MBaud per
serial link.
Each transmit channel accepts preencoded 10-bit trans-
mission characters in an Input Register, serializes each
character, and drives it out a PECL-compatible differential line
driver. Each receive channel accepts a serial data stream at a
differential line receiver, deserializes the stream into 10-bit
characters, optionally frames these characters to the proper
10-bit character boundaries and presents these characters to
an Output register. Figure 1 illustrates typical connections
between independent systems and a CYP(V)15G0402DXB.
The CYV15G0402DXB satisfies the SMPTE-259M and
SMPTE-292M compliance as per the EG34-1999 Pathological
Test Requirements.
10
10
10
10
Serial Links
Serial Links
Independent
Channel
Transceiver
Independent
Channel
Transceiver
10
10
10
10
10
10
Serial Links
Independent
Channel
Transceiver
10
10
10
10
Serial Links
Cable or
Optical
Connections
Independent
Channel
Transceiver
10
10
Note:
Figure 1. CYP(V)15G0402DXB HOTLink II™ System Connections
1. CYV15G0402DXB refers to SMPTE 259M and SMPTE 292M compliant devices. CYP15G0402DXB refers to devices that are not compliant to SMPTE 259M
and SMPTE 292M pathological test requirements. CYP(V)15G0402DXB refers to both devices.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-02057 Rev. *G
Revised March 31, 2005
1 page  
CYP15G0402DXB
CYV15G0402DXB
Pin Configuration (Top View)[2]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
A INC- OUTC- N/C N/C VCC IND- OUTD- GND N/C N/C INA- OUTA- GND N/C N/C VCC INB- OUTB- N/C N/C
B INC+ OUTC+ N/C N/C VCC IND+ OUTD+ GND N/C N/C INA+ OUTA+ GND N/C N/C VCC INB+ OUTB+ N/C N/C
C TDI TMS LPENC LPENB VCC PARCTL SDASEL GND BOE[7] BOE[5] BOE[3] BOE[1] GND GND GND VCC TXRATE RXRATE N/C TDO
D
TCLK TRSTZ LPEND LPENA VCC
RF SPD
MODE SEL
GND BOE[6] BOE[4] BOE[2] BOE[0] GND GND GND
VCC
N/C RXLE N/C
N/C
E
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
F TXPER TXOP TXDC
www.DataSheet4U.com C C [0]
G TXDC TXCKSEL TXDC
[7] [4]
N/C
TXDC
[1]
H GND GND GND GND
BISTLE RXDB RXOP RXDB
[0] B [1]
GND OELE FRAM RXDB
CHAR [3]
GND GND GND GND
J TXDC TXDC TXDC TXDC
[9] [5] [2} [3]
K RXDC RXCLK TXDC LFIC
[4] C- [8]
L RXDC RXCLK TXCLK TXDC
[5] C+ C [6]
M RXDC RXDC RXDC RXDC
[6] [7] [9] [8]
N GND GND GND GND
COMDET RXDB RXDB RXDB
B [2] [7] [4]
RXDB RXDB RXDB RXCLKB
[5] [6] [9] +
RXDB LFIB RXCLK TXDB
[8] B- [6]
TXDB TXDB TXDB TXCLK
[9] [8] [7] B
GND GND GND GND
P RXDC RXDC RXDC RXDC
[3] [2] [1] [0]
R COMDET RXOP TXPER TXOP
CCDD
T
VCC
VCC
VCC
VCC
TXDB
[5]
TXDB
[1]
VCC
TXDB
[4]
TXDB
[0]
VCC
TXDB TXDB
[3] [2]
TXOP TXPER
BB
VCC
VCC
U TXDD TXDD TXDD TXDD VCC RXDD RXDD GND RXOP RFEN REFCLK TXDA GND TXDA TXDA VCC RXDA RXOPA COMDET RXDA
[0] [1] [2] [9] [4] [3] D C - [1] [4] [8] [4] A [0]
V TXDD TXDD TXDD RXDD VCC RXDD RXDD GND COMDET RFEN REFCLK RFEN GND TXDA TXDA VCC RXDA RXDA RXDA RXDA
[3] [4] [8] [8]
[5] [1]
DD + B
[3] [7]
[9] [5] [2] [1]
W TXDD TXDD LFID RXCLK VCC RXDD RXDD GND TXCLKO TXRST TXOPA RFEN GND TXDA TXDA VCC LFIA RXCLKA RXDA RXDA
[5] [7] D– [6] [0]
–
A [2] [6]
– [6] [3]
Y TXDD TXCLK RXDD RXCLK VCC RXDD RXDD GND TXCLKO N/C TXCLK TXPER GND TXDA TXDA VCC TXDA RXCLKA RXDA RXDA
[6] D [9] D+
[7] [2]
+
AA
[0] [5]
[9] + [8] [7]
Note:
2. N/C = Do Not Connect
Document #: 38-02057 Rev. *G
Page 5 of 29
5 Page 
CYP15G0402DXB
CYV15G0402DXB
Pin Descriptions CYP(V)15G0402DXB Quad HOTLink II™ SERDES (continued)
Name
SDASEL
I/O Characteristics Signal Description
Three-level Select[5], Signal Detect Amplitude Level Select. Allows selection of one of three predefined
static configuration amplitude trip points for a valid signal indication, as listed in Table 4.
input
LPENA
LPENB
LPENC
LPEND
LVTTL Input,
asynchronous,
internal pull-down
Loop-Back-Enable. Active HIGH. When asserted (HIGH), the transmit serial data from
the associated channel is internally routed to its respective receiver clock and data
recovery (CDR) circuit. The serial output for the channel where LPENx is active is forced
to differential logic “1”, and serial data inputs for that channel are ignored.
LFIA
LFIB
LFIC
www.DataSheet4LUF.IcDom
LVTTL Output,
Asynchronous
Link Fault Indication Output. Active LOW. LFIx is the logical OR of four internal condi-
tions:
1. Received serial data frequency outside expected range
2. Analog amplitude below expected levels
3. Transition density lower than expected
4. Receive Channel disabled.
TRSTZ
LVCMOS Input,
internal pull-up
Device Reset. Active LOW. Initializes all state machines and counters in the device.
When sampled LOW by the rising edge of REFLCK, this input resets the internal state
machines and sets the Elasticity Buffer pointers to a nominal offset. When the reset is
removed (TRSTZ sampled HIGH by REFCLK↑), the status and data outputs will
become deterministic in fewer than 16 REFCLK cycles.
The BISTLE, OELE, and RXLE latches are reset by TRSTZ.
If the Elasticity Buffer or the Phase Align Buffer are used, TRSTZ should be applied after
power up to initialize the internal pointers into these memory arrays.
JTAG Interface
TMS
LVTTL Input,
internal pull-up
Test Mode Select. Used to control access to the JTAG Test Modes. If maintained high
for >5 TCLK cycles, the JTAG test controller is reset. The TAP controller is also reset
automatically upon application of power to the device.
TCLK
LVTTL Input,
JTAG Test Clock
internal pull-down
TDO
Three-state
LVTTL Output
Test Data Out. JTAG data output buffer which is High-Z while JTAG test mode is not
selected.
TDI
LVTTL Input,
Test Data In. JTAG data input port.
internal pull-up
Power
VCC
GND
+3.3V Power
Signal and Power Ground for all internal circuits.
CYP(V)15G0402DXB HOTLink II SERDES
Operation
The CYP(V)15G0402DXB is a highly configurable device
designed to support reliable transfer of large quantities of data
using high-speed serial links from one or multiple sources to
multiple destinations. This device supports four character-
wide channels.
CYP(V)15G0402DXB Transmit Data Path
Data Path
The transmit path of the CYP(V)15G0402DXB supports four
character-wide data paths. These four data paths are inter-
nally unencoded and require 10-bit input data that may be
pre-encoded or scrambled to achieve sufficient transition
density.
Input Register
The bits in the Input Register for each channel have fixed bit
assignments, as listed in Table 1. Each input register captures
a minimum of 10 bits on each input clock cycle. When parity
checking is enabled, the TXOPx parity input is also captured
in the associated input register.
Input Register Clocking
The transmit Input Registers can be configured to accept data
relative to different clock sources. The selection of the clock
source is controlled by TXCKSEL.
When TXCKSEL = LOW, the Input Registers for all four
transmit channels are clocked by REFCLK↑[4]. When
TXCKSEL = HIGH, the Input Registers for all four transmit
channels are clocked with TXCLKA↑.
When TXCKSEL is MID, TXCLKx↑ is used as the input
register clock for the associated TXDx[9:0] and TXOPx.
Document #: 38-02057 Rev. *G
Page 11 of 29
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| PDF Descargar | [ Datasheet CYV15G0402DXB.PDF ] | |
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