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PDF CYV15G0204TRB Data sheet ( Hoja de datos )
| Número de pieza | CYV15G0204TRB | |
| Descripción | Independent Clock HOTLink IIBT Dual Serializer and Dual Reclocking Deserializer | |
| Fabricantes | Cypress Semiconductor | |
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CYV15G0204TRB
Independent Clock HOTLink II™ Dual
Serializer and Dual Reclocking Deserializer
Features
• Second-generation HOTLink® technology
• Compliant to SMPTE 292M and SMPTE 259M video
standards
• Dual-channel video serializer plus dual channel video
reclocking deserializer
www.DataSheet4U—.co1m95- to 1500-Mbps serial data signaling rate
— Simultaneous operation at different signaling rates
• Supports reception of either 1.485 or 1.485/1.001 Gbps data
rate with the same training clock
• Supports half-rate and full-rate clocking
• Internal phase-locked loops (PLLs) with no external PLL
components
• Selectable differential PECL-compatible serial inputs
— Internal DC-restoration
• Redundant differential PECL-compatible serial outputs
— No external bias resistors required
— Signaling-rate controlled edge-rates
— Internal source termination
• Synchronous LVTTL parallel interface
• JTAG boundary scan
• Built-In Self-Test (BIST) for at-speed link testing
• Link Quality Indicator
— Analog signal detect
— Digital signal detect
• Low-power 2.5W @ 3.3V typical
• Single 3.3V supply
• Thermally enhanced BGA
• Pb-Free package option available
• 0.25μ BiCMOS technology
Functional Description
The CYV15G0204TRB Independent Clock HOTLink II™ Dual
Serializer and Dual Reclocking Deserializer is a point-to-point
or point-to-multipoint communications building block enabling
transfer of data over a variety of high-speed serial links
including SMPTE 292M and SMPTE 259M video applications.
It supports signaling rates in the range of 195 to 1500 Mbps
per serial link. All transmit and receive channels are
independent and can operate simultaneously at different
rates. Each transmit channel accepts 10-bit parallel characters
in an Input Register and converts them to serial data. Each
receive channel accepts serial data and converts it to 10-bit
parallel characters and presents these characters to an Output
Register. The received serial data can also be reclocked and
retransmitted through the reclocker serial outputs. Figure 1
illustrates typical connections between independent video
co-processors and corresponding CYV15G0204TRB chips.
The CYV15G0204TRB satisfies the SMPTE 259M and
SMPTE 292M compliance as per SMPTE EG34-1999 Patho-
logical Test Requirements.
As a second-generation HOTLink device, the
CYV15G0204TRB extends the HOTLink family with enhanced
levels of integration and faster data rates, while maintaining
serial-link compatibility (data and BIST) with other HOTLink
devices. Each transmit (TX) channel of the CYV15G0204TRB
HOTLink II device accepts scrambled 10-bit transmission
characters. These characters are serialized and output from
dual Positive ECL (PECL) compatible differential trans-
mission-line drivers at a bit-rate of either 10- or 20-times the
input reference clock for that channel.
Figure 1. HOTLink II™ System Connections
Independent
Channel
CYV15G0204TRB
Device
Reclocked
Outputs
Independent
Channel
CYV15G0204TRB
Device
10
10
10
10
Serial Links
10
10
10
Reclocked
Outputs
Cypress Semiconductor Corporation
Document #: 38-02101 Rev. *C
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Revised May 2, 2007
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CYV15G0204TRB
Device Configuration and Control Block Diagram
WREN
ADDR[3:0]
DATA[6:0]
www.DataSheet4U.com
Device Configuration
and Control Interface
TXRATE[A..B]
TXCKSEL[A..B]
PABRST[A..B]
TOE[2..1][A..B]
TXBIST[A..B]
RXRATE[C..D]
SDASEL[2..1][C..D][1:0]
TRGRATE[C..D]
RXPLLPD[C..D]
RXBIST[C..D][1:0]
ROE[2..1][C..D]
= Internal Signal
Document #: 38-02101 Rev. *C
Page 5 of 31
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CYV15G0204TRB
Pin Definitions (continued)
CYV15G0204TRB HOTLink II Dual Serializer and Dual Reclocking Deserializer
Name
I/O Characteristics Signal Description
DATA[6:0]
LVTTL input
asynchronous,
internal pull-up
Control Data Bus. The DATA[6:0] bus is the input data bus used to configure the
device. The WREN input writes the values of the DATA[6:0] bus into the latch
specified by address location on the ADDR[3:0] bus.[5] Table 4 on page 16 lists the
configuration latches within the device, and the initialization value of the latches upon
the assertion of RESET. Table 5 on page 18 shows how the latches are mapped in
the device.
Internal Device Configuration Latches
www.DataSheet4RUX.cRoAmTE[C..D]
Internal Latch[6]
SDASEL[2..1][C..D] Internal Latch[6]
[1:0]
Receive Clock Rate Select.
Signal Detect Amplitude Select.
TXCKSEL[A..B] Internal Latch[6]
Transmit Clock Select.
TXRATE[A..B]
Internal Latch[6]
Transmit PLL Clock Rate Select.
TRGRATE[C..D] Internal Latch[6]
Reclocker Output PLL Clock Rate Select.
RXPLLPD[C..D] Internal Latch[6]
Receive Channel Power Control.
RXBIST[C..D][1:0] Internal Latch[6]
Receive Bist Disabled.
TXBIST[A..B]
Internal Latch[6]
Transmit Bist Disabled.
TOE2[A..B]
Internal Latch[6]
Transmitter Differential Serial Output Driver 2 Enable.
TOE1[A..B]
Internal Latch[6]
Transmitter Differential Serial Output Driver 1 Enable.
ROE2[C..D]
Internal Latch[6]
Reclocker Differential Serial Output Driver 2 Enable.
ROE1[C..D]
Internal Latch[6]
Reclocker Differential Serial Output Driver 1 Enable.
PABRSTB[A..B] Internal Latch[6]
Transmit Clock Phase Alignment Buffer Reset.
Factory Test Modes
SCANEN2
LVTTL input,
Factory Test 2. SCANEN2 input is for factory testing only. This input may be left as
internal pull-down a NO CONNECT, or GND only.
TMEN3
LVTTL input,
Factory Test 3. TMEN3 input is for factory testing only. This input may be left as a
internal pull-down NO CONNECT, or GND only.
Analog I/O
TOUTA1±
TOUTB1±
CML Differential
Output
Transmitter Primary Differential Serial Data Output. The transmitter TOUTx1±
PECL-compatible CML outputs (+3.3V referenced) are capable of driving terminated
transmission lines or standard fiber-optic transmitter modules, and must be
AC-coupled for PECL-compatible connections.
TOUTA2±
TOUTB2±
CML Differential
Output
Transmitter Secondary Differential Serial Data Output. The transmitter TOUTx2±
PECL-compatible CML outputs (+3.3V referenced) are capable of driving terminated trans-
mission lines or standard fiber-optic transmitter modules, and must be AC-coupled for
PECL-compatible connections.
ROUTC1±
ROUTD1±
CML Differential
Output
Reclocker Primary Differential Serial Data Output. The reclocker ROUTx1±
PECL-compatible CML outputs (+3.3V referenced) are capable of driving terminated
transmission lines or standard fiber-optic transmitter modules, and must be
AC-coupled for PECL-compatible connections.
ROUTC2±
ROUTD2±
CML Differential
Output
Reclocker Secondary Differential Serial Data Output. The reclocker ROUTx2±
PECL-compatible CML outputs (+3.3V referenced) are capable of driving terminated trans-
mission lines or standard fiber-optic transmitter modules, and must be AC-coupled for
PECL-compatible connections.
INC1±
IND1±
Differential Input
Primary Differential Serial Data Input. The INx1± input accepts the serial data
stream for deserialization. The INx1± serial stream is passed to the receive CDR
circuit to extract the data content when INSELx = HIGH.
Note
6. See Device Configuration and Control Interface for detailed information on the internal latches.
Document #: 38-02101 Rev. *C
Page 11 of 31
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