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PDF CYV15G0203TB Data sheet ( Hoja de datos )

Número de pieza CYV15G0203TB
Descripción Independent Clock Dual HOTLink II Serializer
Fabricantes Cypress Semiconductor 
Logotipo Cypress Semiconductor Logotipo



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No Preview Available ! CYV15G0203TB Hoja de datos, Descripción, Manual

PRELIMINARY
CYV15G0203TB
Independent Clock Dual HOTLink II™ Serializer
Features
• Dual channel video serializer
— 195- to 1500-Mbps serial data signaling rate
— Simultaneous operation at different signaling rates
• Second-generation HOTLink® technology
• Compliant to SMPTE 292M and SMPTE 259M video
www.DataSheet4Us.tcaonmdards
• Supports half-rate and full-rate clocking
• Internal phase-locked loops (PLLs) with no external
PLL components
• Redundant differential PECL-compatible serial outputs
per channel
— No external bias resistors required
— Signaling-rate controlled edge-rates
— Internal source termination
• Synchronous LVTTL parallel interface
• JTAG boundary scan
• Built-In Self-Test (BIST) for at-speed link testing
• Low-power 1.4W @ 3.3V typical
• Single 3.3V supply
• Thermally enhanced BGA
• 0.25µ BiCMOS technology
Functional Description
The CYV15G0203TB Independent Clock Dual HOTLink II™
Serializer is a point-to-point or point-to-multipoint communica-
tions building block enabling transfer of data over a variety of
high-speed serial links including SMPTE 292M and SMPTE
259M video applications. It supports signaling rates in the
range of 195 to 1500 Mbps per serial link. The two channels
are independent and can simultaneously operate at different
rates. Each channel accepts 10-bit parallel characters in an
Input Register and converts them to serial data. Figure 1 illus-
trates typical connections between independent video co-
processors and corresponding CYV15G0203TB Serializer
and CYV15G0204RB Reclocking Deserializer chips.
The CYV15G0203TB satisfies the SMPTE-259M and SMPTE-
292M compliance as per SMPTE EG34-1999 Pathological
Test Requirements.
As a second-generation HOTLink device, the
CYV15G0203TB extends the HOTLink family with enhanced
levels of integration and faster data rates, while maintaining
serial-link compatibility (data, and BIST) with other HOTLink
devices. Each channel of the CYV15G0203TB Dual HOTLink
II device accepts scrambled 10-bit transmission characters.
These characters are serialized and output from dual Positive
ECL (PECL) compatible differential transmission-line drivers
at a bit-rate of either 10- or 20-times the input reference clock
for that channel.
Each channel contains an independent BIST pattern
generator. This BIST hardware allows at-speed testing of the
high-speed serial data paths in each transmit section of this
device, each receive section of a connected HOTLink II
device, and across the interconnecting links.
The CYV15G0203TB is ideal for SMPTE applications where
different data rates and serial interface standards are
necessary for each channel. Some applications include multi-
format routers, switchers, format converters, and cameras.
Reclocked
Output
10
Independent
Channel
CYV15G0203TB
Serializer
10
Serial Links
Independent
Channel
CYV15G0204RB
Reclocking Deserializer
10
10
Reclocked
Output
Figure 1. HOTLink II™ System Connections
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-02105 Rev. **
Revised July 21, 2004

1 page




CYV15G0203TB pdf
Pin Configuration (Bottom View)[1]
PRELIMINARY
CYV15G0203TB
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A
NC
VCC
NC
VCC
VCC
OUT GND GND OUT GND OUT GND GND OUT
A2– A1– B2– B1–
NC
VCC
NC
NC
NC
NC
B
NC
NC
NC
NC
VCC
OUT
A2+
NC GND OUT
A1+
NC
OUT
B2+
NC
GND OUT
B1+
VCC
VCC
NC
VCC
NC
VCC
C
TDO GND TRST NC
VCC
SPD
SELB
NC
GND DATA DATA
[0] [2]
NC
NC GND NC
NC VCC VCC VCC TMS TDI
www.DataSheet4UD.comTMEN3
SCAN
EN2
NC
NC
VCC
NC
GND GND GND DATA DATA GND GND
[1] [3]
NC
VCC
VCC
VCC
VCC RESET TCLK
E VCC VCC VCC VCC
VCC VCC VCC VCC
F NC NC NC NC
NC VCC NC NC
G
NC SPD NC
SELA
NC
H GND GND GND GND
GND GND WREN GND
GND GND GND GND
J NC NC NC NC
GND GND GND GND
K NC NC NC NC
GND GND NC NC
L GND NC NC NC
GND NC NC NC
M GND NC NC NC
NC NC NC NC
N GND GND GND GND
GND GND GND GND
P GND GND GND GND
NC NC NC NC
R VCC VCC VCC VCC
NC NC NC NC
T VCC VCC VCC VCC
VCC VCC VCC VCC
U
NC
NC
VCC
NC
VCC
TX TX GND TX REF ADDR TX GND
DA[8] DA[4]
DA[1] CLKB– [0] DA[9]
NC
NC
VCC
TX
DB[9]
TX
DB[2]
TX
DB[1]
TX
DB[0]
V
NC
NC
NC
NC
VCC
TX TX GND TX REF GND
DA[7] DA[3]
CLKOA CLKB+
NC
GND
NC
NC
VCC
NC
TX TX TX
DB[8] DB[4] DB[3]
W
NC
NC REF NC
CLKA+
VCC
TX TX GND TX
DA[6] DA[2]
ERRA
NC
ADDR ADDR GND
[1] [2]
NC
NC VCC NC
NC TX TX
DB[7] DB[5]
Y
NC
NC
REF TX
CLKA– ERRB
VCC
TX
DA[5]
TX GND
DA[0]
NC
TX
CLKA
NC TX GND
CLKOB
NC
NC VCC NC
NC TX TX
CLKB DB[6]
Document #: 38-02105 Rev. **
Page 5 of 19

5 Page





CYV15G0203TB arduino
PRELIMINARY
CYV15G0203TB
Maximum Ratings
Above which the useful life may be impaired. User guidelines
only, not tested
Storage Temperature .................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage to Ground Potential ............... –0.5V to +3.8V
DC Voltage Applied to LVTTL Outputs
in High-Z State .......................................–0.5V to VCC + 0.5V
Output Current into LVTTL Outputs (LOW)..................60 mA
DC Input Voltage....................................–0.5V to VCC + 0.5V
www.DataSheetC4UY.cVo1m5G0203TB DC Electrical Characteristics
Static Discharge Voltage.......................................... > 2000 V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... > 200 mA
Power-up Requirements
The CYV15G0203TB requires one power-supply. The Voltage
on any input or I/O pin cannot exceed the power pin during
power-up.
Operating Range
Range
Commercial
Ambient Temperature
0°C to +70°C
VCC
+3.3V ±5%
Parameter
Description
Test Conditions
Min.
Max.
Unit
LVTTL-compatible Outputs
VOHT
Output HIGH Voltage
VOLT
Output LOW Voltage
IOST Output Short Circuit Current
IOZL High-Z Output Leakage Current
LVTTL-compatible Inputs
IOH = 4 mA, VCC = Min.
IOL = 4 mA, VCC = Min.
VOUT = 0V[7], VCC = 3.3V
VOUT = 0V, VCC
2.4 V
0.4 V
–20
–100
mA
–20 20 µA
VIHT Input HIGH Voltage
VILT Input LOW Voltage
IIHT Input HIGH Current
IILT Input LOW Current
IIHPDT
Input HIGH Current with internal pull-down
IILPUT
Input LOW Current with internal pull-up
LVDIFF Inputs: REFCLKx±
VDIFF[8]
Input Differential Voltage
VIHHP
Highest Input HIGH Voltage
VILLP
Lowest Input LOW voltage
VCOMREF[9] Common Mode Range
3-Level Inputs
REFCLKx Input, VIN = VCC
Other Inputs, VIN = VCC
REFCLKx Input, VIN = 0.0V
Other Inputs, VIN = 0.0V
VIN = VCC
VIN = 0.0V
2.0
–0.5
400
1.2
0.0
1.0
VCC + 0.3
0.8
1.5
+40
–1.5
–40
+200
–200
V
V
mA
µA
mA
µA
µA
µA
VCC
VCC
VCC/2
VCC – 1.2V
mV
V
V
V
VIHH
Three-Level Input HIGH Voltage
Min. VCC Max.
0.87 * VCC
VCC
VIMM
Three-Level Input MID Voltage
Min. VCC Max.
0.47 * VCC 0.53 * VCC
VILL Three-Level Input LOW Voltage
Min. VCC Max.
0.0 0.13 * VCC
IIHH Input HIGH Current
VIN = VCC
200
IIMM Input MID current
VIN = VCC/2
–50 50
IILL Input LOW current
VIN = GND
–200
Differential CML Serial Outputs: OUTA1±, OUTA2±, OUTB1±, OUTB2±, OUTC1±, OUTC2±, OUTD1±, OUTD2±
V
V
V
µA
µA
µA
VOHC
VOLC
VODIF
Output HIGH Voltage
(Vcc Referenced)
Output LOW Voltage
(VCC Referenced)
Output Differential Voltage
|(OUT+) (OUT)|
100differential load
150differential load
100differential load
150differential load
100differential load
150differential load
VCC – 0.5
VCC – 0.5
VCC – 1.4
VCC – 1.4
450
560
VCC – 0.2
VCC – 0.2
VCC – 0.7
VCC – 0.7
900
1000
V
V
V
V
mV
mV
7. Tested one output at a time, output shorted for less than one second, less than 10% duty cycle.
8. This is the minimum difference in voltage between the true and complement inputs required to ensure detection of a logic-1 or logic-0. A logic-1 exists when
the true (+) input is more positive than the complement () input. A logic-0 exists when the complement () input is more positive than true (+) input.
9. The common mode range defines the allowable range of REFCLKx+ and REFCLKxwhen REFCLKx+ = REFCLKx. This marks the zero-crossing between
the true and complement inputs as the signal switches between a logic-1 and a logic-0.
Document #: 38-02105 Rev. **
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