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PDF CYV15G0201DXB Data sheet ( Hoja de datos )
| Número de pieza | CYV15G0201DXB | |
| Descripción | Dual-channel HOTLink II Transceiver | |
| Fabricantes | Cypress Semiconductor | |
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CYP15G0201DXB
CYV15G0201DXB
Dual-channel HOTLink II™ Transceiver
Features
• Dual channel transceiver for 195 to 1500 MBaud serial
signaling rate
— Aggregate throughput of 12 GBits/second
• Second-generation HOTLink® technology
• Compliant to multiple standards
www.DataSheet4U—.coEmSCON, DVB-ASI, Fibre Channel and Gigabit
Ethernet (IEEE802.3z)
— CYV15G0201DXB also compliant to SMPTE 259M
and SMPTE 292M
— 8B/10B encoded or 10-bit unencoded data
• Selectable parity check/generate
• Selectable dual-channel bonding option
— One 16-bit channels
• Skew alignment support for multiple bytes of offset
• Selectable input/output clocking options
• MultiFrame™ Receive Framer
— Bit and Byte alignment
— Comma or full K28.5 detect
— Single- or multi-byte framer for byte alignment
— Low-latency option
• Synchronous LVTTL parallel interface
• Internal phase-locked loops (PLLs) with no external
PLL components
• Optional Phase-Align Buffer in transmit path
• Optional Elasticity Buffer in receive path
• Dual differential PECL-compatible serial inputs per
channel
— Internal DC-restoration
• Dual differential PECL-compatible serial outputs per
channel
— Source matched for 50Ω transmission lines
— No external bias resistors required
— Signaling-rate controlled edge-rates
• Compatible with
— fiber-optic modules
— copper cables
— circuit board traces
• JTAG boundary scan
• Built-In Self-Test (BIST) for at-speed link testing
• Per-channel Link Quality Indicator
— Analog signal detect
— Digital signal detect
• Low power 1.8W @ 3.3V typical
• Single 3.3V supply
• 196-ball BGA
• 0.25µ BiCMOS technology
Functional Description
The CYP(V)15G0201DXB[1] Dual-channel HOTLink II™
Transceiver is a point-to-point or point-to-multipoint communi-
cations building block allowing the transfer of data over
high-speed serial links (optical fiber, balanced, and unbal-
anced copper transmission lines) at signaling speeds ranging
from 195- to 1500-MBaud per serial link.
The CYV15G0201DXB satisfies the SMPTE 259M and
SMPTE 292M compliance as per the EG34-1999 Pathological
Test Requirements.
10
10
10
10
Serial Links
Serial Links
10
10
10
10
Backplane or
Cabled
Connections
Figure 1. HOTLink II™ System Connections
Note:
1. CYV15G0201DXB refers to SMPTE 259M and SMPTE 292M compliant devices.
CYP15G0201DXB refers to devices not compliant to SMPTE 259M and SMPTE 292M pathological test requirements.
CYP(V)15G0201DXB refers to both devices.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-02058 Rev. *G
Revised January 26, 2004
1 page  
Pin Configuration (Bottom View)[3]
CYP15G0201DXB
CYV15G0201DXB
14 13 12
VCC OUTB1- INB1+
11 10
9
VCC OUTB2- INB2+
8
VCC
BOE[3] OUTB1+ INB1-
VCC OUTB2+ INB2-
NC
BOE[2] SDASEL VCC RFMODE PARCTL SPDSEL GND
VCC VCC INSELA INSELB TDI
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TCLK GND
TMS TRSTZ RXCKSEL TXCKSEL TXPERB TXOPB GND
TXDB[0] TXDB[1] TXDB[2] TXDB[3] TXDB[4] GND
GND
VCC
NC
GND
GND
GND
GND
GND
VCC
NC
GND
GND
GND
GND
GND
TXDB[5] TXDB[6] TXDB[7] TXCTB[1] TXCTB[0] GND
GND
TXCLKB LFIB RXCLKB- RXCLKB+ RXOPB NC
GND
VCC VCC RXDB[7] RXSTB[1] RXSTB[2] SCSEL GND
RXDB[6] RXDB[5] VCC RXSTB[0] NC
TXRST GND
RXDB[4] RXDB[3] RXDB[2] VCC TXCLKO+ REFCLK- NC
VCC RXDB[0] RXDB[1] VCC TXCLKO- REFCLK+ VCC
Note:
3. NC = Do not connect.
7654321
VCC OUTA1- INA1+
VCC OUTA2- INA2+
VCC
A
NC OUTA1+ INA1-
VCC OUTA2+ INA2-
TDO
B
GND RXRATE RXLE LPEN
VCC RFEN
NC
C
GND RXMODE[0] RXMODE[1] TXRATE NC VCC VCC
D
GND
BOE[1] BOE[0] TXMODE[0] TXMODE[1] FRAMCHAR BISTLE
E
GND
GND RXSTA[1] RXSTA[2] RXCLKC+ OELE DECMODE
F
GND
GND
GND
GND
GND
NC
VCC
G
GND
GND
GND
GND
GND
NC
VCC
H
GND
GND
RXDA[2] RXDA[1] RXDA[0] RXOPA RXSTA[0]
J
GND TXCLKA TXDA[4] RXDA[6] RXDA[5] RXDA[4] RXDA[3]
K
GND TXOPA TXDA[3] LFIA RXDA[7] VCC
VCC
L
GND TXPERA TXDA[2] NC
VCC TXCTA[1] RXCLKA-
M
NC NC TXDA[1] VCC TXDA[6] TXCTA[0] RXCLKA+
N
VCC NC TXDA[0] VCC TXDA[5] TXDA[7] VCC
P
Document #: 38-02058 Rev. *G
Page 5 of 46
5 Page 
CYP15G0201DXB
CYV15G0201DXB
Pin Descriptions CYP(V)15G0201DXB Dual HOTLink II Transceiver (continued)
Pin Name I/O Characteristics
Signal Description
OELE
LVTTL Input,
asynchronous,
internal pull-up
Serial Driver Output Enable Latch Enable. Active HIGH. When OELE = HIGH, the signals
on the BOE[3:0] inputs directly control the OUTxy± differential drivers. When the BOE[x]
input is HIGH, the associated OUTxy± differential driver is enabled. When the BOE[x] input
is LOW, the associated OUTxy± differential driver is powered down. When OELE returns
LOW, the last values present on BOE[3:0] are captured in the internal Output Enable Latch.
The specific mapping of BOE[3:0] signals to transmit output enables is listed in Table 9.
RXLE
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LVTTL Input,
asynchronous,
internal pull-up
BISTLE
LVTTL Input,
asynchronous,
internal pull-up
BOE[3:0]
LVTTL Input,
asynchronous,
internal pull-up
LFIA
LFIB
LVTTL Output,
Asynchronous
If the device is reset (TRSTZ is sampled LOW), the latch is reset to disable all outputs.
Receive Channel Power-Control Latch Enable. Active HIGH. When RXLE = HIGH, the
signals on the BOE[3:0] inputs directly control the power enables for the receive PLLs and
analog logic. When the BOE[3:0] input is HIGH, the associated receive channel A and
receive channel B PLL and analog logic are active. When the BOE[3:0] input is LOW, the
associated receive channel A and receive channel B PLL and analog logic are placed in a
non-functional power saving mode. When RXLE returns LOW, the last values present on
BOE[3:0] are captured in the internal RX PLL Enable Latch. The specific mapping of
BOE[3:0] signals to the associated receive channel enables is listed in Table 9. When the
device is reset (TRSTZ is sampled LOW), the latch is reset to disable both receive channels.
Transmit and Receive BIST Latch Enable. Active HIGH. When BISTLE = HIGH, the
signals on the BOE[3:0] inputs directly control the transmit and receive BIST enables. When
the BOE[x] input is LOW, the associated transmit or receive channel is configured to
generate or compare the BIST sequence. When the BOE[x] input is HIGH, the associated
transmit or receive channel is configured for normal data transmission or reception. When
BISTLE returns LOW, the last values present on BOE[3:0] are captured in the internal BIST
Enable Latch. The specific mapping of BOE[3:0] signals to transmit and receive BIST
enables is listed in Table 9. When the latch is closed, if the device is reset (TRSTZ is sampled
LOW), the latch is reset to disable BIST on all transmit and receive channels.
BIST, Serial Output, and Receive Channel Enables. These inputs are passed to and
through the Output Enable Latch when OELE = HIGH, and captured in this latch when
OELE returns LOW. These inputs are passed to and through the BIST Enable Latch when
BISTLE = HIGH, and captured in this latch when BISTLE returns LOW. These inputs are
passed to and through the Receive Channel Enable Latch when RXLE = HIGH, and
captured in this latch when RXLE returns LOW.
Link Fault Indication Output. Active LOW. LFIx is the logical OR of four internal conditions:
1. Received serial data frequency outside expected range.
JTAG Interface
TMS
LVTTL Input,
internal pull-up
TCLK
TDO
TDI
Power
VCC
GND
LVTTL Input,
internal pull-down
3-State
LVTTL Output
LVTTL Input,
internal pull-up
2. Analog amplitude below expected levels.
3. Transition density lower than expected.
4. Receive Channel disabled.
Test Mode Select. Used to control access to the JTAG Test Modes. If maintained HIGH for
>5 TCLK cycles, the JTAG test controller is reset. The TAP controller is also reset automat-
ically upon application of power to the device.
JTAG Test Clock.
Test Data Out. JTAG data output buffer which is High-Z while JTAG test mode is not
selected.
Test Data In. JTAG data input port.
+3.3V power.
Signal and Power Ground for all internal circuits.
Document #: 38-02058 Rev. *G
Page 11 of 46
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