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PDF CYV15G0104TRB Data sheet ( Hoja de datos )
| Número de pieza | CYV15G0104TRB | |
| Descripción | Independent Clock HOTLink II Serializer and Reclocking Deserializer | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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PRELIMINARY
CYV15G0104TRB
Independent Clock HOTLink II™ Serializer and
Reclocking Deserializer
Features
• Single channel video serializer plus single channel
video reclocking deserializer
— 195- to 1500-Mbps serial data signaling rate
— Simultaneous operation at different signaling rates
• Second-generation HOTLink® technology
www.DataSheet•4UCs.tcoaomnmdpaliradnst to SMPTE 292M and SMPTE 259M video
• Supports reception of either 1.485 or 1.485/1.001 Gbps
data rate with the same training clock
• Internal phase-locked loops (PLLs) with no external
PLL components
• Supports half-rate and full-rate clocking
• Selectable differential PECL-compatible serial inputs
— Internal DC-restoration
• Redundant differential PECL-compatible serial outputs
— No external bias resistors required
— Internal source termination
— Signaling-rate controlled edge-rates
• Synchronous LVTTL parallel interface
• JTAG boundary scan
• Built-In Self-Test (BIST) for at-speed link testing
• Link Quality Indicator
— Analog signal detect
— Digital signal detect
• Low-power 1.8W @ 3.3V typical
• Single 3.3V supply
• Thermally enhanced BGA
• 0.25µ BiCMOS technology
Functional Description
The CYV15G0104TRB Independent Clock HOTLink II™
Serializer and Reclocking Deserializer is a point-to-point or
point-to-multipoint communications building block enabling
transfer of data over a variety of high-speed serial links
including SMPTE 292M and SMPTE 259M video applications.
It supports signaling rates in the range of 195 to 1500 Mbps
per serial link. The transmit and receive channels are
independent and can operate simultaneously at different
rates. The transmit channel accepts 10-bit parallel characters
in an Input Register and converts them to serial data. The
receive channel accepts serial data and converts it to 10-bit
parallel characters and presents these characters to an Output
Register. The received serial data can also be reclocked and
retransmitted through the reclocker serial outputs. Figure 1
illustrates typical connections between independent video co-
processors and corresponding CYV15G0104TRB chips.
The CYV15G0104TRB satisfies the SMPTE 259M and
SMPTE 292M compliance as per SMPTE EG34-1999 Patho-
logical Test Requirements.
As a second-generation HOTLink device, the
CYV15G0104TRB extends the HOTLink family with enhanced
levels of integration and faster data rates, while maintaining
serial-link compatibility (data and BIST) with other HOTLink
devices. The transmit (TX) channel of the CYV15G0104TRB
HOTLink II device accepts scrambled 10-bit transmission
characters. These characters are serialized and output from
dual Positive ECL (PECL) compatible differential trans-
mission-line drivers at a bit-rate of either 10- or 20-times the
input reference clock for that channel.
The receive (RX) channel of the CYV15G0104TRB HOTLink
II device accepts a serial bit-stream from one of two selectable
PECL-compatible differential line receivers, and using a
completely integrated Clock and Data Recovery PLL, recovers
the timing information necessary for data reconstruction. The
recovered bit-stream is reclocked and retransmitted through
the reclocker serial outputs. Also, the recovered serial data is
deserialized and presented to the destination host system.
The transmit and receive channels contain an independent
BIST pattern generator and checker, respectively. This BIST
hardware allows at-speed testing of the high-speed serial data
paths in each transmit and receive section, and across the
interconnecting links.
10
10
Independent
Channel
CYV15G0104TRB
Device
Reclocked
Output
Serial
Links
Reclocked
Output
Independent
Channel
CYV15G0104TRB
Device
10
10
Figure 1. HOTLink II™ System Connections
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-02100 Rev. **
Revised July 14, 2004
1 page  
Pin Configuration (Top View)[1]
PRELIMINARY
CYV15G0104TRB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
A
NC NC NC NC VCC
B
VCC NC VCC NC VCC
C
TDI TMS VCC VCC VCC
D
www.DataSheet4U.comTCLK RESET VCC INSELA VCC
E
VCC VCC VCC VCC
NC TOUT GND GND TOUT IN ROUT GND IN ROUT
B1–
B2– A1– A1–
A2– A2–
VCC
TOUT
B1+
GND
NC
TOUT
B2+
IN
A1+
ROUT GND
A1+
IN
A2+
ROUT
A2+
NC NC GND DATA DATA DATA DATA GND NC SPD
[6] [4] [2] [0]
SELB
ULCA NC GND DATA DATA DATA GND GND GND NC
[5] [3] [1]
VCC
VCC
VCC
VCC
VCC NC VCC NC
NC NC NC NC
LDTD TRST GND TDO
EN
NC
VCC
SCAN TMEN3
EN2
VCC VCC VCC VCC
F
NC NC VCC NC
VCC NC NC NC
G
GND WREN GND GND
H
GND GND GND GND
NC NC SPD NC
SELA
GND GND GND GND
J
GND GND GND GND
NC NC NC NC
K
NC NC GND GND
NC NC NC NC
L
NC NC NC GND
NC NC NC GND
M
NC NC NC NC
NC NC NC GND
N
GND GND GND GND
GND GND GND GND
P
NC NC NC NC
GND GND GND GND
R
NC NC NC NC
VCC VCC VCC VCC
T
VCC VCC VCC VCC
VCC VCC VCC VCC
U
TX TX
DB[0] DB[1]
TX TX
DB[2] DB[9]
VCC
NC
NC
GND GND ADDR REF GND GND GND
[0] CLKB–
VCC
VCC
RX
DA[4]
VCC
BIST RX
STA DA[0]
V
TX TX TX
DB[3] DB[4] DB[8]
NC
VCC
NC
NC
GND
NC
GND REF RE GND GND
CLKB+ CLKOA
VCC
VCC
RX RX RX RX
DA[9] DA[5] DA[2] DA[1]
W
TX TX NC
DB[5] DB[7]
NC
VCC
NC
NC
GND ADDR ADDR RX REPDO GND GND
[2] [1] CLKA+ A
VCC
VCC
LFIA TRG RX
RX
CLKA+ DA[6] DA[3]
Y
TX TX NC
DB[6] CLKB
NC
VCC
NC
NC
GND TX NC
CLKOB
GND RX GND GND
CLKA–
VCC
VCC
TX TRG RX
ERRB CLKA– DA[8]
RX
DA[7]
1. NC = Do not connect.
Document #: 38-02100 Rev. **
Page 5 of 28
5 Page 
PRELIMINARY
CYV15G0104TRB
CYV15G0104TRB Transmit Data Path
Input Register
The parallel input bus TXDB[9:0] can be clocked in using
TXCLKB (TXCKSELB = 0) or REFCLKB (TXCKSELB = 1).
Phase-Align Buffer
Data from the Input Register is passed to the Phase-Align
Buffer, when the TXDB[9:0] input register is clocked using
TXCLKBA (TXCKSELB = 0) or when REFCLKB is a half-rate
clock (TXCKSELB = 1 and TXRATEB = 1). When the
TXDB[9:0] input register is clocked using REFCLKB±
(TXCKSELA = 1) and REFCLKB± is a full-rate clock
(TXRATEB = 0), the associated Phase Alignment Buffer in the
www.DataSheet4raUn.csommit path is bypassed. These buffers are used to absorb
clock phase differences between the TXCLKB input clock and
the internal character clock for that channel.
Once initialized, TXCLKB is allowed to drift in phase as much
as ±180 degrees. If the input phase of TXCLKB drifts beyond
the handling capacity of the Phase Align Buffer, TXERRB is
asserted to indicate the loss of data, and remains asserted
until the Phase Align Buffer is initialized. The phase of
TXCLKB relative to its internal character rate clock is initialized
when the configuration latch PABRSTB is written as 0. When
the associated TXERRB is deasserted, the Phase Align Buffer
is initialized and input characters are correctly captured.
If the phase offset, between the initialized location of the input
clock and REFCLKB, exceeds the skew handling capabilities
of the Phase-Align Buffer, an error is reported on that
channel’s TXERRB output. This output indicates an error
continuously until the Phase-Align Buffer for that channel is
reset. While the error remains active, the transmitter for that
channel outputs a continuous “1001111000” character to
indicate to the remote receiver that an error condition is
present in the link.
Transmit BIST
The transmit channel contains an internal pattern generator
that can be used to validate both the link and device operation.
This generator is enabled by the TXBISTB latch via the device
configuration interface. When enabled, a register in the
transmit channel becomes a signature pattern generator by
logically converting to a Linear Feedback Shift Register
(LFSR). This LFSR generates a 511-character sequence. This
provides a predictable yet pseudo-random sequence that can
be matched to an identical LFSR in the attached Receiver(s).
A device reset (RESET sampled LOW) presets the BIST
Enable Latches to disable BIST on all channels.
All data present at the TXDB[9:0] inputs are ignored when
BIST is active on that channel.
Transmit PLL Clock Multiplier
The Transmit PLL Clock Multiplier accepts a character-rate or
half-character-rate external clock at the REFCLKB± input, and
that clock is multiplied by 10 or 20 (as selected by TXRATEB)
to generate a bit-rate clock for use by the transmit shifter. It
also provides a character-rate clock used by the transmit
paths, and outputs this character rate clock as TXCLKOB.
The clock multiplier PLL can accept a REFCLKB± input
between 19.5 MHz and 150 MHz, however, this clock range is
limited by the operating mode of the CYV15G0104TRB clock
multiplier (TXRATEB) and by the level on the SPDSELB input.
SPDSELB is a 3-level select[4] input that selects one of three
operating ranges for the serial data outputs of the transmit
channel. The operating serial signaling-rate and allowable
range of REFCLKB± frequencies are listed in Table 1.
Table 1. Operating Speed Settings
SPDSELB
LOW
MID (Open)
HIGH
TXRATEB
1
0
1
0
1
0
REFCLKB±
Frequency
(MHz)
reserved
19.5 – 40
20 – 40
40 – 80
40 – 75
80 – 150
Signaling
Rate (Mbps)
195 – 400
400 – 800
800 – 1500
The REFCLKB± inputs are differential inputs with each input
internally biased to 1.4V. If the REFCLKB+ input is connected
to a TTL, LVTTL, or LVCMOS clock source, the input signal is
recognized when it passes through the internally biased
reference point. When driven by a single-ended TTL, LVTTL,
or LVCMOS clock source, connect the clock source to either
the true or complement REFCLKB input, and leave the
alternate REFCLKB input open (floating).
When both the REFCLKB+ and REFCLKB– inputs are
connected, the clock source must be a differential clock. This
can either be a differential LVPECL clock that is DC-or
AC-coupled or a differential LVTTL or LVCMOS clock.
By connecting the REFCLKB– input to an external voltage
source, it is possible to adjust the reference point of the
REFCLKB+ input for alternate logic levels. When doing so, it
is necessary to ensure that the input differential crossing point
remains within the parametric range supported by the input.
Transmit Serial Output Drivers
The serial output interface drivers use differential Current
Mode Logic (CML) drivers to provide source-matched drivers
for 50Ω transmission lines. These drivers accept data from the
transmit shifter. These drivers have signal swings equivalent
to that of standard PECL drivers, and are capable of driving
AC-coupled optical modules or transmission lines.
Transmit Channels Enabled
Each driver can be enabled or disabled separately via the
device configuration interface.
When a driver is disabled via the configuration interface, it is
internally powered down to reduce device power. If both
transmit serial drivers are in this disabled state, the transmitter
internal logic for that channel is also powered down. A device
reset (RESET sampled LOW) disables all output drivers.
Note. When the disabled transmit channel (i.e., both outputs
disabled) is re-enabled:
• the data on the transmit serial outputs may not meet all
timing specifications for up to 250 µs
• the state of the phase-align buffer cannot be guaranteed,
and a phase-align reset is required if the phase-align buffer
is used
Document #: 38-02100 Rev. **
Page 11 of 28
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet CYV15G0104TRB.PDF ] | |
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