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PDF PI49FCT3805A Data sheet ( Hoja de datos )
| Número de pieza | PI49FCT3805A | |
| Descripción | 3.3V Fast CMOS Buffer/Clock Driver | |
| Fabricantes | Pericom Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de PI49FCT3805A (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
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PI49FCT3805/PI49FCT3806
PI49FCT3805A/PI49FCT3806A
PI49FCT3805B/PI49FCT3806B
PI49FCT3805C/PI49FCT3806C1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122
3.3V Fast CMOS Buffer/Clock Driver
Features
3.3VversionofPI49FCT805/806
Extremely low output skew: 0.5ns
Monitor ouput pin
Clock busing wih 3-state control
TTL inpu and CMOS output compatible
Industrial operation at40°C to 85°C
Extremely low static power (1mW, typ.)
Hysteresis on all inputs
Packages available:
www.DataS h2200e--eppiitnn413U50.00c--ommmiill wwiiddee
SOIC (S)
QSOP (Q)
20-pin 209-mil wide SSOP (H)
Device models available on request
Product Description
Pericom Semiconductors PI49FCT series of logic circuits are
produced using the Companys advanced submicron CMOS
technology, achieving industry leading speed grades.
The PI49FCT3805 is a 3.3V non-inverting clock driver and the
PI49FCT3806 is a 3.3V inverting clock driver designed with two
independent groups of buffers. These buffers have 3-state Output
Enable inputs (active LOW) with a 1-in, 5-out configuration per
group. Each clock driver consist of two banks of drivers, driving five
outputs each from a standard TTL compatible CMOS input.
PI49FCT3805 Logic Block Diagram
PI49FCT3806 Logic Block Diagram
OEA
INA
INB
OEB
5
OA0-4
OEA
INA
5
OB0-4
MON
INB
OEB
5
OA0-4
5
OB0-4
MON
1 PS7007B 01/13/99
1 page  
PI49FCT3805/3806
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Switching Characteristics over Operating Range
3805/3806
3805A/3806A
Parameters
Description
Condition(1)
Com.
Com.
Min. Max Min. Max
tPLH Propagation Delay
tPHL INA to OAN, INB to OBN
1.5 6.5 1.5 5.8
tPZH Output Enable Time
tPZL OEA to OAN, OEB to OBN
1.5 8.0 1.5 8.0
tPHZ Output Disable Time
tPLZ OEA to OAN, OEB to OBN
1.5 7.0 1.5 7.0
tS K (o)(3)
Skew between two outputs of
same package (Same transition)
CL = 50pF
RL = 500Ω
0.7
0.7
Skew between opposite
www.DataStShKe(p)e(3t)4U.tcraonsmition (tPHL-tPLH) of the
same output
1.0 0.7
tS K (t)(3)
Skew between two outputs of
different package at same
temperature (Same transition)
1.5 1.2
Note:
1. See test circuit and waveforms
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew measured at worst cast temperature (max. temp).
3805B/3806B
Com.
Min. Max
1.5 5.0
1.5 6.5
1.5 6.0
0.5
0.5
1.0
3805C/3806C
Com.
Min. Max
1.5 4.5
1.5 6.2
1.5 5.0
0.5
0.5
0.8
Units
ns
Tests Circuits for All Outputs(1) , except for FIN >100 MHz
6.0V
V CC
Pulse
Generator
V IN
D.U.T.
V OUT
RT
Ω500
50pF
CL
Ω500
Switch Position
Test
Disable LOW
Enable LOW
Disable HIGH
Enable HIGH
All Other Inputs
Switch
6V
GND
Open
DEFINITIONS:
CL = Load capacitance: includes jig and probe
capacitance.
RT = Termination resistance: should be equal to
ZOUT of the Pulse Generator.
5 PS7007B 01/13/99
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet PI49FCT3805A.PDF ] | |
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