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PDF MT45W2MW16BFB Data sheet ( Hoja de datos )
| Número de pieza | MT45W2MW16BFB | |
| Descripción | (MT45W2MW16BFB / MT45W4MW16BFB) Burst Cellularram Memory | |
| Fabricantes | Micron Semiconductor | |
| Logotipo |  |
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BURST
CellularRAMTM
ADVANCE‡
4 MEG x 16, 2 MEG x 16
ASYNC/PAGE/BURST CellularRAM MEMORY
MT45W4MW16BFB
MT45W2MW16BFB
For the latest data sheet, please refer to Micron’s Web site:
www.micron.com/datasheets.
Features
• Single device supports asynchronous, page, and
burst operations
• VCC, VCCQ Voltages
1.70V–1.95V VCC
1.70V–2.25V VCCQ (Option W)
• Random Access Time: 70ns
• Burst Mode Write Access
Continuous burst
• Burst Mode Read Access
4, 8, or 16 words, or continuous burst
MAX clock rate: 104 MHz (tCLK = 9.62ns)
Burst initial latency: 39ns (4 clocks) @ 104 MHz
tACLK: 6.5ns @ 104 MHz
• Page Mode Read Access
Sixteen-word page size
Interpage read access: 70ns
Intrapage read access: 20ns
• Low Power Consumption
Asynchronous READ < 25mA
Intrapage READ < 15mA
Initial access, burst READ: (39ns [4 clocks]
@ 104 MHz) < 35mA
Continuous burst READ < 15mA
Standby: 90µA (32Mb), 100µA (64Mb)
Deep power-down < 10µA
• Low-Power Features
Temperature Compensated Refresh (TCR)
Partial Array Refresh (PAR)
Deep Power-Down (DPD) Mode
Options
• VCC Core Voltage Supply:
1.80V – MT45WxMx16BFB
• VCCQ I/O Voltage
3.0V – MT45WxML16BFB
2.5V – MT45WxMV16BFB
1.8V – MT45WxMW16BFB
• Timing
60ns access
70ns access
85ns access
• Frequency
66 MHz
104 MHz
Marking
W
(contact factory)
(contact factory)
W
(contact factory)
-70
-85
1
6
Figure 1: Ball Assignment 54-Ball FBGA
1234
A
LB# OE#
A0
A1
56
A2 CRE
B
DQ8 UB#
A3
A4
CE# DQ0
C DQ9 DQ10 A5 A6 DQ1 DQ2
D
VSSQ DQ11 A17
A7
DQ3
VCC
E VCCQ DQ12 A21 A16 DQ4 VSS
F DQ14 DQ13 A14 A15 DQ5 DQ6
G DQ15 A19 A12 A13 WE# DQ7
H A18 A8 A9 A10 A11 A20
J WAIT CLK ADV# NC NC NC
Top View
(Ball Down)
NOTE:
See Table 1 on page 6 for ball descriptions, and
Figure 40 on page 50 for 54-ball mechanical drawing.
Options (continued)
Marking
• Configuration:
4 Meg x 16
2 Meg x 16
• Package
54-ball FBGA
• Operating Temperature Range
Wireless (-25°C to +85°C)
Industrial (-40°C to +85°C)
MT45W4Mx16BFB
MT45W2Mx16BFB
FB
WT
IT (contact factory)
NOTE:
A part marking guide for the FBGA devices can be found
on Micron’s Web site: www. micron.com/numberguide
Part Number Example:
MT45W2MW16BFB-701WT
09005aef80be2036/09005aef80be1fbd
Burst CellularRAM.fm - Rev. A 7/03 EN
1 ©2003 Micron Technology, Inc. All Rights Reserved.
‡PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.
1 page  
www.DataSheet4U.com
ADVANCE
4 MEG x 16, 2 MEG x 16
ASYNC/PAGE/BURST CellularRAM MEMORY
General Description
Micron CellularRAM™ products are high-speed,
CMOS dynamic random access memories developed
for low-power, portable applications. The
MT45W4MW16BFB is a 64Mb device organized as 4
Meg x 16 bits; the MT45W2MW16BFB is a 32Mb
device organized as 2 Meg x 16 bits. These devices
include an industry-standard burst mode Flash inter-
face that dramatically increases read/write bandwidth
compared with other low-power SRAM or Pseudo
SRAM offerings.
To operate seamlessly on a burst Flash bus, Cellular-
RAM products have incorporated a transparent self-
refresh mechanism. The hidden refresh requires no
additional support from the system memory controller
and has no significant impact on device read/write
performance.
Two user-accessible control registers define device
operation. The bus configuration register (BCR)
defines how the CellularRAM device interacts with the
system memory bus and is nearly identical to its coun-
terpart on burst mode Flash devices.
The refresh configuration register (RCR) is used to
control how refresh is performed on the DRAM array.
These registers are automatically loaded with default
settings during power-up and can be updated anytime
during normal operation.
Special attention has been focused on standby cur-
rent consumption during self refresh. CellularRAM
products include three system-accessible mechanisms
used to minimize standby current. Partial array refresh
(PAR) limits refresh to only that part of the DRAM array
that contains essential data. Temperature compen-
sated refresh (TCR) is used to adjust the refresh rate
according to the case temperature. The refresh rate
can be decreased at lower temperatures to minimize
current consumption during standby. Deep power-
down (DPD) halts the refresh operation altogether and
is used when no vital information is stored in the
device. These three refresh mechanisms are adjusted
through the RCR.
Figure 2: Functional Block Diagram – 4 Meg x 16 and 2 Meg x 16
A[20:0]
(for 32Mb)
A[21:0]
(for 64Mb)
Address Decode
Logic
Refresh Configuration
Register (RCR)
2,048K x 16
(4,096K x 16)
DRAM
MEMORY
ARRAY
Input/
Output
MUX
and
Buffers
DQ[7:0]
DQ[15:8]
CE#
WE#
OE#
CLK
ADV#
CRE
WAIT
LB#
UB#
Control
Logic
Bus Configuration
Register (BCR)
NOTE:
Functional block diagrams illustrate simplified device operation. See truth table, ball descriptions, and timing
diagrams for detailed information.
09005aef80be2036/09005aef80be1fbd
Burst CellularRAM.fm - Rev. A 7/03 EN
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All Rights Reserved.
5 Page 
www.DataSheet4U.com
CLK
A[21:0]
ADV#
CE#
OE#
WE#
WAIT
DQ[15:0]
LB#/UB#
ADVANCE
4 MEG x 16, 2 MEG x 16
ASYNC/PAGE/BURST CellularRAM MEMORY
Figure 7: Burst Mode READ (4-word burst)1
ADDRESS
VALID
Latency Code 2 (3 clocks)
READ Burst Identified
(WE# = HIGH)
D[0]
D[1]
D[2] D[3]
DON’T CARE
CLK
A[21:0]
ADV#
CE#
OE#
Figure 8: Burst Mode WRITE (4-word burst)1
ADDRESS
VALID
Latency Code 2 (3 clocks)
WE#
WAIT
DQ[15:0]
LB#/UB#
D[0]
D[1]
D[2] D[3]
WRITE Burst Identified
(WE# = LOW)
DON’T CARE
NOTE:
1. Nondefault BCR settings: Latency code two (three clocks); WAIT active LOW; Hold data one clock; WAIT asserted during delay.
09005aef80be2036/09005aef80be1fbd
Burst CellularRAM.fm - Rev. A 7/03 EN
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All Rights Reserved.
11 Page | ||
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