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PDF MT45W2MW16PFA Data sheet ( Hoja de datos )
| Número de pieza | MT45W2MW16PFA | |
| Descripción | (MT45WxMx16PFA) Async Cellularram Memory | |
| Fabricantes | Micron Semiconductor | |
| Logotipo |  |
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PRELIMINARY‡
4 MEG x 16, 2 MEG x 16
ASYNC/PAGE CellularRAM MEMORY
ASYNCHRONOUS
CellularRAMTM
MT45W4MW16PFA MT45W2MW16PFA
MT45W4MV16PFA MT45W2MV16PFA
MT45W4ML16PFA MT45W2ML16PFA
For the latest data sheet, please refer to Micron’s Web site:
www.micron.com/datasheets
Features
• Asynchronous and Page Mode interface
• Random Access Time: 70ns, 85ns
• Page Mode Read Access
Sixteen-word page size
Interpage read access: 70ns, 85ns
Intrapage read access: 20ns, 25ns
• VCC, VCCQ Voltages
1.70V–1.95V VCC
1.70V–2.25V VCCQ (Option W)
2.30V–2.70V VCCQ (Option V)
2.70V–3.30V VCCQ (Option L)
• Low Power Consumption
Asynchronous READ < 25mA
Intrapage READ < 15mA
Standby: 90µA (32Mb), 100µA (64Mb)
Deep Power-Down < 10µA
• Low-Power Features
Temperature Compensated Refresh (TCR)
Partial Array Refresh (PAR)
Deep Power-Down (DPD) Mode
Figure 1: 48-Ball FBGA
123456
A LB# OE# A0 A1 A2 ZZ#
B DQ8 UB# A3 A4 CE# DQ0
C DQ9 DQ10 A5 A6 DQ1 DQ2
D
VSSQ DQ11 A17
A7
DQ3
VCC
E VCCQ DQ12 A21 A16 DQ4 VSS
F DQ14 DQ13 A14 A15 DQ5 DQ6
G DQ15 A19 A12 A13 WE# DQ7
H A18 A8 A9 A10 A11 A20
Options
• VCC Core Voltage Supply
1.8V – MT45WxMx16PFA
• VCCQ I/O Voltage
3.0V – MT45WxML16PFA
2.5V – MT45WxMV16PFA
1.8V – MT45WxMW16PFA
• Access Time
60ns
70ns
85ns
• Configuration
4 Meg x 16
2 Meg x 16
• Package
48-ball FBGA
• Operating Temperature Range
Wireless (-25°C to +85°C)
Industrial (-40°C to +85°C)
Marking
W
L
V
W
(contact factory)
-70
-85
MT45W4Mx16PFA
MT45W2Mx16PFA
FA
WT
IT (contact factory)
Top View
(Bump Down)
NOTE:
See Table 1 on page 3 for Ball Descriptions. See Figure 18
on page 22 for the 48-ball mechanical drawing.
NOTE:
A part marking guide for the FBGA devices can be found
on Micron’s Web site: www.micron.com/numberguide.
Part Number Example:
MT45W2ML16PFA-70WT
09005aef80be1f7f
AsyncCellularRAM.fm - Rev. A 7/03 EN
1 ©2003 Micron Technology, Inc. All Rights Reserved.
‡PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.
1 page  
www.DataSheet4U.com
PRELIMINARY
4 MEG x 16, 2 MEG x 16
ASYNC/PAGE CellularRAM MEMORY
Functional Description
In general, the MT45W4Mx16PFA device and the
MT45W2Mx16PFA device are high-density alternatives
to SRAM and Pseudo SRAM products, popular in low-
power, portable applications. The MT45W4Mx16PFA
contains 67,108,864 bits organized as 4,194,304
addresses by 16 bits. The MT45W2Mx16PFA contains
33,554,432 bits organized as 2,097,152 addresses by 16
bits. These devices include the industry-standard, asyn-
chronous memory interface found on other low-power
SRAM or Pseudo SRAM offerings. Page mode accesses
are also included as a bandwidth-enhancing extension
to the asynchronous read protocol.
Power-Up Initialization
CellularRAM products include an on-chip voltage
sensor that is used to launch the power-up initializa-
tion process. Initialization will load the CR with its
default settings. VCC and VCCQ must be applied simul-
taneously, and when they reach a stable level above
1.70V, the device will require 150µs to complete its self-
initialization process (see Figure 3 below). During the
initialization period, CE# should remain HIGH. When
initialization is complete, the device is ready for nor-
mal operation. At power-up, the CR is set to 0070h.
Asynchronous Mode
CellularRAM products power up in the asynchro-
nous operating mode. This mode uses the industry-
standard SRAM control interface (CE#, OE#, WE#, LB#/
UB#). READ operations (Figure 4) are initiated by
bringing CE#, OE#, and LB#/UB# LOW while keeping
WE# HIGH. Valid data will be driven out of the I/Os
after the specified access time has elapsed. WRITE
operations (Figure 5) occur when CE#, WE#, and LB#/
UB# are driven LOW. During WRITE operations, the
level of OE# is a “Don't Care”; WE# will override OE#.
The data to be written will be latched on the rising edge
of CE#, WE#, or LB#/UB# (whichever occurs first).
Figure 4: READ Operation
CE#
OE#
WE#
ADDRESS
ADDRESS VALID
Figure 3: Power-Up Initialization
Timing
Vcc
VccQ
Vcc = 1.7V
tPU > 150µs
Device Initialization
Device ready for
normal operation
Bus Operating Modes
The MT45W4Mx16PFA and the MT45W2Mx16PFA
CellularRAM products incorporate the industry-stan-
dard, asynchronous interface found on other low-
power SRAM or Pseudo SRAM offerings. This bus
interface supports asynchronous READ and WRITE
operations as well as the bandwidth-enhancing page
mode READ operation. The specific interface that is
supported is defined by the value loaded into the CR.
DATA
LB#/UB#
Data Valid
tRC = READ Cycle Time
DON’T CARE
Figure 5: WRITE Operation
CE#
OE#
WE#
ADDRESS
ADDRESS VALID
DATA
Data Valid
LB#/UB#
tWC = WRITE Cycle Time
DON’T CARE
09005aef80be1f7f
AsyncCellularRAM.fm - Rev. A 7/03 EN
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All Rights Reserved.
5 Page 
www.DataSheet4U.com
PRELIMINARY
4 MEG x 16, 2 MEG x 16
ASYNC/PAGE CellularRAM MEMORY
Table 8: Temperature Compensated Refresh Specifications and Conditions
DESCRIPTION
Temperature
Compensated
Refresh Standby
Current
CONDITIONS
VIN = VCCQ or 0V,
Chip Disabled
SYMBOL
ITCR
DENSITY
64Mb
32Mb
MAX CASE
TEMPERATURES
+85°C
+70°C
+45°C
+15°C
+85°C
+70°C
+45°C
+15°C
TYP
MAX
100
TBD
TBD
50
90
TBD
TBD
50
UNITS
µA
µA
µA
µA
µA
µA
µA
µA
NOTE:
1. ITCR (MAX) values measured with FULL ARRAY refresh.
2. This device assumes a standby mode if the chip is disabled (CE# HIGH). It will also automatically go into a standby
mode whenever all input signals are quiescent (not toggling), regardless of the state of CE#, LB#, and UB#. In order
to achieve low standby current, all inputs must be either VCCQ or VSS.
Table 9: Partial Array Refresh Specifications and Conditions
DESCRIPTION
Partial Array Refresh
Current
CONDITIONS
VIN = VCCQ or 0V
ZZ# = LOW
CR[4] = 1
SYMBOL DENSITY
IPAR 64Mb
32Mb
ARRAY
PARTITION
Full
3/4
1/2
1/4
0
Full
3/4
1/2
1/4
0
NOTE:
IPAR (MAX) values measured with TCR set to 85°C.
TYP MAX UNITS
100 µA
TBD µA
TBD µA
TBD µA
50 µA
90 µA
TBD µA
TBD µA
TBD µA
50 µA
Table 10: Deep Power-Down Specifications and Conditions
DESCRIPTION
Deep Power-Down
CONDITIONS
VIN = VCCQ or 0V; +25°C
ZZ# = LOW
CR[4] = 0
SYMBOL
IZZ
TYP
MAX
10
UNITS
µA
09005aef80be1f7f
AsyncCellularRAM.fm - Rev. A 7/03 EN
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All Rights Reserved.
11 Page | ||
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