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PDF MC68833 Data sheet ( Hoja de datos )
| Número de pieza | MC68833 | |
| Descripción | Twisted Pair Interface | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MC68833 (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
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SEMICONDUCTOR TECHNICAL DATA
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Twisted Pair Interface
for 100Base-TX Local Area Networks
Overview
100Base–TX is a LAN standard under IEEE auspices. The twisted pair
cable connecting two stations can be up to 100 meters in length. Users
are encouraged to refer to the pertinent IEEE 802.3 standard documents
for further information.
Introduction
The MC68833 Twisted Pair Interface Chip (TPIC) is a transceiver
capable of transmitting and receiving MLT3 encoded datastreams, as well
as handling clock and data recovery. The TPIC implements the lower
portion of the physical layer (PHY) functions of the Fast Ethernet
standard and, with its Auto Negotiation Fast Link Pulse “Pass Through”
capability, is well suited for 100Base–TX applications. It performs a
five–bit parallel to serial conversion during transmission, as well as a
five–bit serial to parallel conversion during reception.
MC68833
FA SUFFIX
TQFP PACKAGE
CASE 931–02
MC68833 Features
• Supports Twisted Pair Media
• Supports MLT–3 Line Code
• Selectable Auto Negotiation mode has FLP and NLP “Pass–Through” Capability
• Controlled Twisted Pair Output Transition Times May Eliminate Need for Transmit Filter
• Adaptive Receive Equalization supports TP line lengths of 0 to 100 meters
• TP Receiver Includes Circuitry Which Enables Error Free Reception of Data Distorted with Base Line Wander
• Twisted Pair (TP) Transceiver Complies with ANSI X3T9.5 TP–PMD Standard and the IEEE 802.3 100Base–TX Ethernet
Draft Standard
• Meets Jitter Requirements of ANSI X3T9.5 TP–PMD
• Physical Layer Support for Fast Ethernet
• Digital Phase–Locked Loop (DPLL) Provides Run Length Immunity
• Transmit Off Capability for True Quiet Line State
• Uses a 25 Mhz External Frequency Reference
• Converts Received Serial Bit Stream to Five–Bit Parallel Form
• Recovers 125 Mhz Clock from Incoming Serial MLT3 Data Stream
• Generates 25 Mhz Receive Clock
• Small Number of Passive External Components Required
• Selectable Low Power Mode
• Loop Back Capability
• Single +5V Power Supply
• Utilizes 0.8uM BiCMOS Technology
• 10mM X 10mM, 64 Pin, TQFP Package (Power Enhanced Leadframe Package)
This document contains information on a product under development. Motorola reserves the right to change or
discontinue this product without notice.
4/95
© Motorola, Inc. 1995
REV 0
1 page  
www.DataSheet4U.com
MC68833
Table 3. Elasticity Link Manager (MAC) Interface Pins (continued)
Pin No.
Pin Name
Pin
Type
Pin Description
58 LB
I Loopback Enable
TTL When low, this input enables Transmitter–Receiver loopback capability, which causes
data appearing at the Transmit Data Bus Inputs (TDATAx) to be fed to the Receive Data
Bus Outputs (RDATAx) and the Signal Detect output (SD) to be forced high.
While in the Loopback mode, the MAC interface will not receive any data from the RDL
and RDH inputs, however, the TDIS input must be forced low to prevent transmit data
from appearing on the TDL and TDH outputs.
59 TDATA4
60 TDATA3
61 TDATA2
62 TDATA1
63 TDATA0
I Transmit Data Bus Inputs
TTL These inputs accept data from the MC68833’s MAC interface which is to be transmitted to
the attached media. The data appearing at each input may change at a 25 Mbps rate.
TDATA4 is transmitted on the media first. Also, when AUTONG is low, the Fast Link
Pulses (FLP) generated from the off–chip Auto Negotiation function must be present on
TDATA4 in order to be transmitted over the media.
Table 4. Clock Pin
Pin No.
Pin Name
46 TCLKIN
Pin
Type
I
TTL
Pin Description
Transmit Clock Input
Users must connect a 25MHz reference clock to this input.
Table 5. External Component Connection Pins
Pin No.
Pin Name
Pin
Type
Pin Description
8
RREFTPT
X
Twisted Pair Transmitter External Reference Resistor Connection Pin
An external precision resistor must be connected between this pin and ground to set the
transmit output current amplitude.
To meet the transmit signal levels specified by the ANSI X3T9.5 TP–PMD specification,
RREFTPT should be set to 2KΩ ±1%. This value of RREFTPT yields an output current of
+/– 40mA. For 100 ohm characteristic impedance UTP applications, this current results in
a 1.0V peak differential output voltage.
20 C1
21 C2
X Twisted Pair Adaptive Equalizer Feedback Capacitor Connection Pins
The external capacitor connected to these pins controls the time constant of the adaptive
receive equalizer. The recommended value is 400pF.
25
TPRECB
X
Twisted Pair Receiver Bias Resistor Connection Pin
The external precision resistor connected to this pin and ground establishes an internal
reference current. This resistor should be set to a value of 3KΩ ±1%.
TIMING SOLUTIONS
BR1333 — REV 4
MOTOROLA
5
5 Page 
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MC68833
TDH/L
(Differential)
tTPT1
90%
10%
tTPT3
90%
tTPT2
10%
tTPT4
tTPT5
0.5V
Figure 6. TDH/L Differential Twisted Pair Transmit Output Timing Characteristics
(NOTE: Specification established by design and laboratory characterization)
Parallel Interface Timing (See Figure 8)
Parameter
Symbol
Test Conditions
RSCLK Period
tPI1
RSCLK Time Low
tPI2
1
RSCLK Time High
tPI3
1
Time to RDATA Invalid
tPI4
Time to RDATA Valid
tPI5
TCLKIN Period
tPI6
TCLKIN Time Low
tPI7
TCLKIN Time High
tPI8
TDATA Setup Time
tPI10
2
TDATA Hold Time
tPI11
2
1. This parameter is specified with the receiver operating at 125 MHz.
2. This is with respect to TCLKIN
Min Typ Max Unit
36 40 44 nS
18 22 nS
18 22 nS
8 nS
32 nS
39 41 nS
18 22 nS
18 22 nS
12 40 nS
0 28 nS
TIMING SOLUTIONS
BR1333 — REV 4
MOTOROLA
11
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