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PDF BUK9609-55A Data sheet ( Hoja de datos )
| Número de pieza | BUK9609-55A | |
| Descripción | (BUK9x09-55A) TrenchMOS logic level FET | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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BUK95/9609-55A
TrenchMOS™ logic level FET
Rev. 01 — 21 February 2002
Product data
1. Description
N-channel enhancement mode field-effect power transistor in a plastic package using
TrenchMOS™ technology, featuring very low on-state resistance.
Product availability:
BUK9509-55A in SOT78 (TO-220AB)
BUK9609-55A in SOT404 (D2-PAK).
2. Features
s TrenchMOS™ technology
s Q101 compliant
s 175 °C rated
s Logic level compatible.
3. Applications
s Automotive and general purpose power switching:
x 12 V and 24 V loads
x Motors, lamps and solenoids.
4. Pinning information
Table 1: Pinning - SOT78 and SOT404, simplified outline and symbol
Pin Description
Simplified outline
1 gate (g)
2 drain (d)
mb
[1]
mb
3 source (s)
mb mounting base;
connected to drain (d)
MBK106
123
SOT78 (TO-220AB)
2
1 3 MBK116
SOT404 (D2-PAK)
[1] It is not possible to make connection to pin 2 of the SOT404 package.
Symbol
g
MBB076
d
s
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Philips Semiconductors
BUK95/9609-55A
TrenchMOS™ logic level FET
8. Characteristics
Table 5: Characteristics
Tj = 25 °C unless otherwise specified.
Symbol Parameter
Conditions
Static characteristics
V(BR)DSS
VGS(th)
drain-source breakdown
voltage
ID = 0.25 mA; VGS = 0 V
Tj = 25 °C
Tj = −55 °C
gate-source threshold voltage ID = 1 mA; VDS = VGS;
Figure 9
IDSS
IGSS
RDSon
drain-source leakage current
gate-source leakage current
drain-source on-state
resistance
Tj = 25 °C
Tj = 175 °C
Tj = −55 °C
VDS = 55 V; VGS = 0 V
Tj = 25 °C
Tj = 175 °C
VGS = ±10 V; VDS = 0 V
VGS = 5 V; ID = 25 A;
Figure 7 and 8
Dynamic characteristics
Tj = 25 °C
Tj = 175 °C
VGS = 4.5 V; ID = 25 A
VGS = 10 V; ID = 25 A
Qg(tot)
Qgs
Qgd
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
Ld
total gate charge
gate-to-source charge
gate-to-drain (Miller) charge
input capacitance
output capacitance
reverse transfer capacitance
turn-on delay time
rise time
turn-off delay time
fall time
internal drain inductance
VGS = 5 V; VDD = 44 V;
ID = 25 A; Figure 14
VGS = 0 V; VDS = 25 V;
f = 1 MHz; Figure 12
VDD = 30 V; RL = 1.2 Ω;
VGS = 5 V; RG = 10 Ω
from drain lead 6 mm from
package to centre of die
from contact screw on
mounting base to centre of
die SOT78
from upper edge of drain
mounting base to centre of
die SOT404
Ls internal source inductance from source lead to source
bond pad
Min
55
50
1
0.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
9397 750 09229
Product data
Rev. 01 — 21 February 2002
Typ Max Unit
--V
--V
1.5 2
--
- 2.3
0.05 10
- 500
2 100
V
V
V
µA
µA
nA
7.6
-
-
6.4
60
9
29
3475
570
360
33
149
197
131
4.5
3.5
9
18
10
8
-
-
-
4633
682
493
-
-
-
-
-
-
mΩ
mΩ
mΩ
mΩ
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
nH
nH
2.5 -
nH
7.5 -
nH
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
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Philips Semiconductors
10. Soldering
handbook, full pagewidth
1.50
2.25 2.15
8.15 8.35
1.50
4.60
4.85
7.95
0.30
3.00
solder lands
solder resist
occupied area
solder paste
Dimensions in mm.
Fig 18. Reflow soldering footprint for SOT404.
BUK95/9609-55A
TrenchMOS™ logic level FET
10.85
10.60
10.50
7.50
7.40
1.70
8.275
5.40
8.075
0.20
5.08
1.20
1.30
1.55
MSD057
9397 750 09229
Product data
Rev. 01 — 21 February 2002
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
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