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PDF BUK9E06-55B Data sheet ( Hoja de datos )
| Número de pieza | BUK9E06-55B | |
| Descripción | (BUK9x06-55B) N-channel TrenchMOSTM logic level FET | |
| Fabricantes | NXP Semiconductors | |
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BUK95/96/9E06-55B
N-channel TrenchMOS™ logic level FET
Rev. 03 — 30 November 2004
Product data sheet
1. Product profile
1.1 General description
N-channel enhancement mode field-effect power transistor in a plastic package using
Philips High-Performance Automotive (HPA) TrenchMOS™ technology, featuring very low
on-state resistance.
1.2 Features
s TrenchMOS™ technology
s 175 °C rated
s Q101 compliant
s Logic level compatible.
1.3 Applications
s Automotive systems
s Motors, lamps and solenoids
s 12 V and 24 V loads
s General purpose power switching.
1.4 Quick reference data
s EDS(AL)S ≤ 679 mJ
s ID ≤ 75 A
s RDSon = 5.1 mΩ (typ)
s Ptot ≤ 258 W.
2. Pinning information
Table 1: Pinning
Pin Description
Simplified outline
1 gate (G)
2 drain (D)
[1] mb
3 source (S)
mb mounting base;
connected to drain (D)
mb
Symbol
mb D
G
mbb076 S
123
SOT78 (TO-220AB)
2
13
SOT404 (D2-PAK)
[1] It is not possible to make a connection to pin 2 of the SOT404 package.
123
SOT226 (I2-PAK)
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Philips Semiconductors
BUK95/96/9E06-55B
N-channel TrenchMOS™ logic level FET
6. Characteristics
Table 5: Characteristics
Tj = 25 °C unless otherwise specified.
Symbol Parameter
Static characteristics
V(BR)DSS drain-source breakdown voltage
VGS(th) gate-source threshold voltage
IDSS drain-source leakage current
IGSS
RDSon
gate-source leakage current
drain-source on-state resistance
Dynamic characteristics
Qg(tot)
Qgs
Qgd
Vplat
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
Ld
total gate charge
gate-source charge
gate-drain (Miller) charge
plateau voltage
input capacitance
output capacitance
reverse transfer capacitance
turn-on delay time
rise time
turn-off delay time
fall time
internal drain inductance
Ls internal source inductance
Conditions
ID = 250 µA; VGS = 0 V
Tj = 25 °C
Tj = −55 °C
ID = 1 mA; VDS = VGS; Figure 9 and 10
Tj = 25 °C
Tj = 175 °C
Tj = −55 °C
VDS = 55 V; VGS = 0 V
Tj = 25 °C
Tj = 175 °C
VGS = ±15 V; VDS = 0 V
VGS = 5 V; ID = 25 A; Figure 6 and 8
Tj = 25 °C
Tj = 175 °C
VGS = 4.5 V; ID = 25 A; Figure 6 and 8
VGS = 10 V; ID = 25 A; Figure 6 and 8
ID = 25 A; VDD = 44 V; VGS = 5 V;
Figure 14 and 16
VGS = 0 V; VDS = 25 V; f = 1 MHz;
Figure 12
VDS = 30 V; RL = 1.2 Ω;
VGS = 5 V; RG = 10 Ω
from drain lead 6 mm from package to
center of die
from contact screw on mounting base to
center of die SOT78
from upper edge of drain mounting base
to center of die SOT404/SOT226
from source lead to source bonding pad
Min Typ Max Unit
55 - - V
50 - - V
1.1 1.5 2
V
0.5 - - V
- - 2.3 V
-
0.02 1
µA
- - 500 µA
- 2 100 nA
- 5.1 6.0 mΩ
- - 12 mΩ
- - 6.4 mΩ
- 4.8 5.4 mΩ
- 60 - nC
- 11 - nC
- 22 - nC
- 2.4 - V
- 5 674 7565 pF
- 755 906 pF
- 255 350 pF
- 37 - ns
- 95 - ns
- 117 - ns
- 106 - ns
- 4.5 - nH
- 3.5 - nH
- 2.5 - nH
- 7.5 - nH
9397 750 13519
Product data sheet
Rev. 03 — 30 November 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
5 of 15
5 Page 
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Philips Semiconductors
BUK95/96/9E06-55B
N-channel TrenchMOS™ logic level FET
Plastic single-ended package (Philips version of I2-PAK); low-profile 3 lead TO-220AB
SOT226
D1 E
D
L2
b1
L
L1
123
ee
b
A
A1
mounting
base
Q
c
0 5 10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT A
A1 b
b1
c
D
max
D1
E
e
mm 4.5 1.40 0.85 1.3 0.7
4.1 1.27 0.60 1.0 0.4
11
1.6
1.2
10.3
9.7
2.54
Note
1. Terminals in this zone are not tinned.
OUTLINE
VERSION
SOT226
REFERENCES
IEC
JEDEC
JEITA
low-profile
3-lead TO-220AB
L
15.0
13.5
L1
3.30
2.79
L2 (1)
max
3
Q
2.6
2.2
EUROPEAN
PROJECTION
Fig 19. Package outline SOT226 (I2-PAK).
ISSUE DATE
03-10-14
04-02-24
9397 750 13519
Product data sheet
Rev. 03 — 30 November 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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