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PDF SII1161 Data sheet ( Hoja de datos )
| Número de pieza | SII1161 | |
| Descripción | PanelLink Receiver | |
| Fabricantes | Silicon image | |
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Hay una vista previa y un enlace de descarga de SII1161 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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®
Technology
SiI 1161
PanelLink Receiver
Data Sheet
Document # SiI-DS-0096-D
1 page  
www.DaStiaISh1e1e6t41UP.caomnelLink Receiver
Data Sheet
June 2005
General Description
The SiI 1161 receiver uses PanelLink Digital
technology to support high-resolution displays up to
UXGA (25-165MHz). This receiver supports up to true
color panels (24 bits per pixel, 16M colors) with both
one and two pixels per clock.
All PanelLink products are designed on a scaleable
CMOS architecture, ensuring support for future
performance enhancements while maintaining the
same logical interface. System designers can be
assured that the interface will be stable through a
number of technology and performance generations.
PanelLink Digital technology simplifies PC and display
interface design by resolving many of the system level
issues associated with high-speed mixed signal
design, providing the system designer with a digital
interface solution that is quicker to market and lower in
cost.
Features
• Supports 10 meter cables at UXGA speed
• I2C port for dynamic optimization of settings to
compensate for long cables and/or poor quality
transmitters
• Flexible output drive controls to optimize timings
for all possible configurations
• 3.3V operation
• Time staggered data output for reduced ground
bounce and lower EMI
• Sync Detect feature for DVI “Hot Plugging”
• ESD tolerant to 5kV (HBM) on all pins
• Compliant with DVI 1.0
• Guaranteed interoperability with DVI-compliant
transmitters
• Low power standby mode; automatic entry into
standby mode with clock detect circuitry
• Pb-free packaging (see page 41).
SiI 1161 Pin Diagram
ODD 8-bits RED
ODD 8-bits GREEN
ODD 8-bits BLUE
OGND
QO23
OVCC
AGND
RX2+
RX2-
AVCC
AGND
AVCC
RX1+
RX1-
AGND
AVCC
AGND
RX0+
RX0-
AGND
RXC+
RXC-
AVCC
EXT_RES
PVCC
PGND
MODE
SCL
(OCK_INV)
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
CONFIG. PINS
SiI 1161
100-Pin
TQFP
(Top View)
PWR
MGMT
EVEN 8-bits BLUE
50 QO1
49 QO0
48 HSYNC
47 VSYNC
46 DE
45 OGND
44
ODCK
OUTPUT
CLOCK
43 OVCC
42 CTL3
41 CTL2
40 CTL1
39 GND
38 VCC
37 QE23
36 QE22
35 QE21
34 QE20
33 QE19
32 QE18
31 QE17
30 QE16
29 OVCC
28 OGND
27 QE15
26 QE14
EVEN 8-bits GREEN
SiI-DS-0096-D
5 Page 
www.DaSDtiaaISt1ah1eS6eth14eUPe.catonmelLink Receiver
The output drive specifications in the Compatible mode are equivalent to the drive on the SiI 161B part.
Table 3. SiI 161B Mode DC Specifications
Strap option: ST=0 (Low Drive Strength)
Parameter
Data and Controls
IOHD Output High Drive
IOLD Output Low Drive
ODCK and DE
IOHC Output High Drive
IOLC Output Low Drive
Conditions
ST VOUT CL
Limits (mA)
Min Typ Max
0 2.4V 5pF 3.8
0 0.8V 5pF 5.5
0 0.4V 5pF 3.2
0 2.4V 10pF 7.5
0 0.8V 10pF 11.1
0 0.4V 10pF 6.2
Notes
1
2
3
4
Strap option: ST=1 (High Drive Strength)
Parameter
Conditions
Limits (mA)
ST VOUT CL
Min Typ Max
Data and Controls
IOHD Output High Drive 1 2.4V 10pF 7.4
IOLD Output Low Drive
1 0.8V 10pF 11.1
1 0.4V 10pF 6.3
ODCK and DE
IOHC Output High Drive 1 2.4V 20pF 14.7
IOLC Output Low Drive
1 0.8V 20pF 21.2
1 0.4V 20pF 12.3
Notes
1. Output loading is equivalent to one or two CMOS input loads.
2. 0.8V corresponds to LVTTL VIN(max).
3. 0.4V corresponds to LVCMOS VIN(max).
4. Output loading is equivalent to two or four CMOS input loads.
Notes
1
2
3
4
7 SiI-DS-0096-D
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SII1161.PDF ] | |
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