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PDF LC89052T Data sheet ( Hoja de datos )
| Número de pieza | LC89052T | |
| Descripción | Digital Audio Interface Receiver | |
| Fabricantes | Sanyo Semicon Device | |
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Ordering number : ENN7457
CMOS LSI
LC89052T
Digital Audio Interface Receiver
1. Overview
The LC89052T is an audio LSI that demodulates
according to the data format for the data transferred
between digital audio devices via the IEC 60958/61937
and EIAJ CP-1201. It supports sampling frequencies of
up to 192kHz and output data lengths up to 28 bits.
Despite it is compact and made in a low cost, the
LC89052T includes a built-in oscillator and serial data
input circuits and allows the system microcontroller to
read the sub-code Q data and channel status. It supports
low-power modes that allow low-voltage operation. It
also supports a lower power mode, which is suitable for
application that requires long battery life, such as cell
phones, PDAs, and portable audio devices.
3. Package Dimensions
unit: mm
3260A
[ LC89052T ]
6.5
24 13
1 0.5
(0.5)
0.2212
0.15
SANYO:TSSOP24(225mil)
2. Features
• Incorporates a built-in PLL circuit to synchronize with transferred bi-phase mark signal.
• Can receive input with sampling frequencies of 32kHz to 192kHz.
• Can set the upper limit of sampling frequency of received data.
• Can receive input data of specific sampling frequencies.
• Outputs the following clocks: fs, 64fs, 128fs, 256fs, 384fs, and 512fs.
• Contains a built-in oscillation amplifier that can construct a oscillation circuit. An external clock can be also provided.
• Outputs an externally input clock signal that can be used as the A/D converter clock when the PLL is unlocked.
• Maintains the continuity of the output clock when the clock is switched.
• Equipped with a serial digital audio data input pin that can be configured for a demodulated signal output.
• Can output up to 28 bits of data, and also supports output of I2S and input NRZ data.
• Can output bi-phase mark signal synchronized with the 128fs bit clock.
• Provides an output pin for the channel status bit 1 non-PCM data detection bit.
• Provides an output pin for the channel status emphasis detection bit.
• Supports a lower-power mode.
Continued on next page.
71003 SI IM No.7457-1/42
1 page  
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7. Electrical Characteristics
7.1 Absolute Maximum Ratings
LC89052T
Parameter
Table 7.1 Absolute Maximum Ratings at AGND = DGND = 0V
Symbol
Conditions
Ratings
Maximum supply voltage
Maximum supply voltage
Input voltage 1
Input voltage 2
Output voltage
Storage temperature
AVDD max
DVDD max
VIN1
VIN2
VOUT
Tstg
7-1-1
7-1-2
7-1-3
7-1-4
7-1-5
–0.3 to 4.6
–0.3 to 4.6
–0.3 to 3.9
–0.3 to 5.8
–0.3 to 3.9
–55 to 125
Operating temperature
Topg
–30 to 70
Maximum output current
Ii, IOUT
7-1-6
±20
7-1-1 :
7-1-2 :
7-1-3 :
7-1-4 :
7-1-5 :
7-1-6 :
AVDD pin.
DVDD pin.
XIN pin.
_____
RXIN, SDIN, PD, CE, CL, and__D_I_p_i_ns._____
XOUT, ERROR, DO, E/INT, AUDIO, UGPI, CKOUT, BCK, LRCK, and DATAO pins.
Per single input or output pin.
unit
V
V
V
V
V
°C
°C
mA
7.2 Recommended Operating Conditions
Parameter
Table 7.2 Recommended Operating Conditions
Symbol
Conditions
min
Supply voltage 1
Supply voltage 2
Input voltage range 1
Input voltage range 2
Operating temperature
AVDD, DVDD
AVDD, DVDD
VIN1
VIN2
Vopg
7-2-1
7-2-2
7-2-3
7-2-4
2.7
3.0
0
0
–30
7-2-1 : PLLCK [1:0] = "00" or PLLCK [1:0] = "01"
7-2-2 : PLLCK [1:0] = "10" or PLLCK [1:0] = "11"
7-2-3 : XIN pin
_____
7-2-4 : RXIN, SDIN, PD, CE, CL, and DI pins
typ
3.3
3.3
3.3
3.3
max
3.6
3.6
3.6
5.5
70
unit
V
V
V
V
°C
7.3 Input and Output Pin Capacitances
Table 7.3 Input and Output Pin Capacitances
Parameter
Symbol
Conditions
min
Input pins
Output pins
CIN
COUT
7-3-1
7-3-1
7-3-1 : AVDD = DVDD = VIN1 = VIN2 = 0 V, Ta = 25°C, f = 1MHz
typ
max
10
10
unit
pF
pF
No.7457-5/42
5 Page 
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LC89052T
8.3 Clocks
8.3.1 PLL (LPF)
• The LC89052T incorporates a VCO (Voltage Controlled Oscillator) that can synchronize with sampling frequencies
of 30kHz to 195kHz.
• The locking frequency is selected with PLLCK[1:0]. The VCO circuit can be stopped with PLLOPR.
• The range of input data that can be received differs depending on the settings of PLLCK[1:0].
• The (512/2)fs for the PLLCK[1:0] = "11" in the table below is the state where the PLL itself is synchronized with the
512fs clock, but the clock signal output from the CKOUT pin is 1/2 of the PLL locked frequency, which is 256fs.
See the chapter on the of output clock for further information.
• We recommend the 256fs setting with PLLCK[1:0] = "00" for the systems such as portable equipment that need to
restrain the consumption electric power. We also recommend the 512fs setting with PLLCK[1:0] = "10" or the
(512/2)fs with PLLCK[1:0] = "11" for the systems such as AV amplifiers that require improved performance.
PLLCK1
0
0
1
1
Table 8.3 Input Data Reception Ranges and PLL Lock Frequency Settings
PLLCK0
PLL lock frequency
Input data reception range
0 256fs
30k to 195kHz
1 384fs
30k to 108kHz
0 512fs
30k to 108kHz
1 (512/2)fs
30k to 108kHz
• LPF is the PLL loop filter connection pin. Use the correct recommended resistance and capacitance as values listed in
the table below according to the PLLCK[1:0] settings.
LPF
R0 C1
C0
PLLCK1
0
0
1
1
PLLCK0
0
1
0
1
R0
150Ω
150Ω
Figure 8.2 PLL Loop Filter Configuration
C0
0.047µF
0.068µF
C1
0.0068µF
0.0047µF
No.7457-11/42
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