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PDF STG4259 Data sheet ( Hoja de datos )
| Número de pieza | STG4259 | |
| Descripción | Low voltage 0.3 Ohm max dual SPDT switch | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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STG4259
Low voltage 0.3Ω max dual SPDT switch
with break-before-make feature and 15KV ESD protection
Features
■ Wide operating voltage range:
VCC (Opr) = 1.65 V to 4.8 V
■ Low power dissipation:
ICC = 0.2 µA (max) at TA = 85°C
■ Low ON resistance VIN = 0V:
– RON = 0.4 Ω (max TA = 25ºC) at
VCC = 2.25 V
– RON = 0.35 Ω (max TA = 25ºC) at
VCC = 3.0 V
– RON = 0.30 Ω (max TA = 25ºC) at
VCC = 4.3 V
■ Separate supply voltage for switch and control
pin
■ Separate control pin for each switch
■ Latch-up performance exceeds 100 mA per
JESD 78, class II
■ ESD performance tested on common channels
(D1 and D2 pins)
– 9 kV IEC-61000-4-2 ESD, contact
discharge
– 15 kV IEC-61000-4-2 ESD, air gap
discharge
■ ESD performance tested on all other pins
– 8 kV IEC-61000-4-2 ESD, contact
discharge
– 500 V machine model (JESD22 A115-A)
– 1500 V charged-device model (JESD22
C101)
– 8 kV IEC-61000-4-2 ESD, air gap
discharge
Flip-Chip11
Description
The STG4259 is a high-speed CMOS low voltage
dual analog SPDT (single pole dual throw) switch
or 2:1 multiplexer/ demultiplexer switch fabricated
in silicon gate C2MOS technology. It is designed
to operate from 1.65 V to 4.8 V, making this device
ideal for portable applications. It offers low ON
resistance (0.30 Ω) at VCC = 4.3 V. The SEL
inputs are provided to control the switches.
The switch S1 is ON (connected to common port
D) when the SEL input is held high and OFF (high
impedance state exists between the two ports)
when SEL is held low; the switch S2 is ON (it is
connected to common port D) when the SEL input
is held low and OFF (high impedance state exist
between the two ports) when SEL is held high.
Additional key features are fast switching speed,
break-before-make delay time and ultra low power
consumption. All inputs and outputs are equipped
with protection circuits against static discharge,
giving them ESD immunity and transient excess
voltage.
Table 1. Device summary
Order code
Package
Packing
STG4259BJR
Flip-Chip11
Tape and Reel
August 2007
Rev 4
1/19
www.st.com
1 page  
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STG4259
2 Maximum rating
Maximum rating
Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 4.
Symbol
Absolute maximum ratings
Parameter
VCC Supply voltage
VL Logic supply voltage
VI DC input voltage
VIC DC control input voltage
VO DC output voltage
IIKC DC input diode current on control pin (VSEL< 0V)
IIK DC input diode current (VSEL< 0V)
IOK DC output diode current
IO DC output current
IOP
DC output current peak (pulse at 1ms, 10% duty
cycle)
ICC or
IGND
PD
DC VCC or ground current
Power dissipation at TA = 70ºC (1)
Tstg Storage temperature
TL Lead temperature (10 sec)
1. Derate above 70ºC by 18.5mW/C
Value
-0.5 to 5.5
-0.5 to 5.5
-0.5 to VCC + 0.5
-0.5 to VL + 0.5
-0.5 to VCC + 0.5
- 50
± 50
± 20
± 300
± 500
± 100
500
-50 to 105
260
Unit
V
V
V
V
V
mA
mA
mA
mA
mA
mA
mW
°C
°C
5/19
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STG4259
Figure 9. Test circuit
Test circuits
Note: 1 CL = 5/35pF or equivalent: (includes jig capacitance)
2 RL = 50Ω or equivalent
3 RT = ZOUT of pulse generator (typically 50Ω)
Figure 10. Break-before-make time delay
11/19
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet STG4259.PDF ] | |
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