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PDF LTC6082 Data sheet ( Hoja de datos )
| Número de pieza | LTC6082 | |
| Descripción | (LTC6081 / LTC6082) Precision Quad CMOS Rail-to-Rail Input/Output Amplifier | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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FEATURES
■ Maximum Offset Voltage: 70μV (25°C)
■ Maximum Offset Drift: 0.8μV/°C
■ Maximum Input Bias: 1pA (25°C) 40pA (TA ≤ 85°C)
■ Open Loop Voltage Gain: 120dB Typ
■ Gain Bandwidth Product: 3.6MHz
■ CMRR: 100dB Min
■ PSRR: 98dB Min
■ 0.1Hz to 10Hz Noise: 1.3μVP-P
■ Supply Current: 330μA
■ Rail-to-Rail Inputs and Outputs
■ Unity Gain Stable
■ 2.7V to 5.5V Operation Voltage
■ Dual LTC6081 in 8-Lead MSOP and 10-Lead DFN10
Packages; Quad LTC6082 in 16-Lead SSOP and DFN
Packages
APPLICATIONS
■ Photodiode Amplifier
■ Strain Gauge
■ High Impedance Sensor Amplifier
■ Microvolt Accuracy Threshold Detection
■ Instrumentation Amplifiers
■ Thermocouple Amplifiers
LTC6081/LTC6082
Precision Dual/Quad
CMOS Rail-to-Rail Input/
Output Amplifiers
DESCRIPTION
The LTC®6081/LTC6082 are dual/quad low offset, low drift,
low noise CMOS operational amplifiers with rail-to-rail
input/output swing.
The 70μV maximum offset, 1pA input bias current, 120dB
open loop gain and 1.3μVP-P 0.1Hz to 10Hz noise make
it perfect for precision signal conditioning. The LTC6081/
LTC6082 features 100dB CMRR and 98dB PSRR.
Each amplifier consumes only 330μA of current on a 3V
supply. The 10-lead DFN has an independent shutdown
function that reduces each amplifier’s supply current
to 1μA.
LTC6081/LTC6082 is specified for power supply voltages
of 3V and 5V from –40°C to 125°C. The dual LTC6081 is
available in 8-lead MSOP and 10-lead DFN10 packages.
The quad LTC6082 is available in 16-lead SSOP and DFN
packages.
, LTC, LT and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
Shock Sensor Amplifier (Accelerometer)
MURATA
PKGS-00LD
770pF
0° SENSOR
8.2pF
2M
1G 3.9pF
2M
3.9pF
1M
V+ 0.1μF
+
1/2
LTC6081
–
V– 0.1μF
1M
VOUT = 109mV/g
BW ~ 2.2kHz
10k
47pF
60812 TA01
VOS Drift Histogram
30
LTC6081MS8
TA = –40°C TO 125°C
25 VS = 3V
VCM = 0.5V
20
15
10
5
0
–0.20
–0.10 0
0.10
VOSDRIFT (μV/°C)
0.20 0.30
60812 TA01b
60812f
1
1 page  
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LTC6081/LTC6082
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Test conditions are V+ = 3V, V– = 0V, VCM = 0.5V unless otherwise noted.
C, I SUFFIXES
H SUFFIX
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX MIN TYP MAX UNITS
Shutdown Logic
⎯S⎯H⎯D⎯N High
⎯S⎯H⎯D⎯N Low
THD Total Harmonic Distortion f = 10kHz, V+ = 3V, VOUT = 1VP-P, RL = 10k
●2
●
2
0.8
0.8
–90 –90
V
V
dB
tON Turn-On Time
V⎯S⎯H⎯D⎯N = 0.8V to 2V
10 10 μs
tOFF Turn-Off Time
⎯S⎯H⎯D⎯N Pin Current
V⎯S⎯H⎯D⎯N = 2V to 0.8V
V⎯S⎯H⎯D⎯N = 0V
2
●2
2
μs
μA
The ● denotes
conditions are
the specifications which apply over
V+ = 5V, V– = 0V, VCM = 0.5V unless
the full operating
otherwise noted.
temperature
range,
otherwise
specifications
are
at
TA
=
25°C.
Test
C, I SUFFIXES
H SUFFIX
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX MIN TYP MAX UNITS
VOS Offset Voltage
ΔVOS ⁄ΔT Input Offset Voltage Drift
(Note 8)
LTC6081MS8, LTC6082GN
LTC6081MS8, LTC6082GN
LTC6081DD, LTC6082DHC
LTC6081DD, LTC6082DHC
VCM = 0.5V
VCM = 0.5V
VCM = 0.5V
VCM = 0.5V
–70
● –90
–70
● –90
70 –70
90 –90
70
90
70 μV
90 μV
μV
μV
● ±0.2 ±0.8
±0.2 ±0.8 μV/°C
IB Input Bias Current
0.2
● 40
0.2
500
pA
pA
IOS Input Offset Current
0.1
● 15
0.1
100
pA
pA
en Input Referred Noise
f = 1kHz
0.1Hz to 10Hz
In Input Noise Current Density
(Note 7)
Input Common Mode Range
13 13 nV/√Hz
1.3 1.3 μVP-P
0.5 0.5 fA/√Hz
● V–
V+ V–
V+ V
CDIFF Differential Input Capacitance
CCM Common Mode Input
Capacitance
3 3 pF
7 7 pF
CMRR
PSRR
Common Mode Rejection
Ratio
VCM = 0V to 3.5V
VCM = 0V to 3.5V
VCM = 0V to 5V
Power Supply Rejection Ratio VS = 2.7V to 5.5V
100
● 95
● 86
98
● 96
110
110
95
110
100 110
94 110
86 95
98 110
96
dB
dB
dB
dB
dB
VOUT Output Voltage, High, Either No Load
Output Pin (Referred to V+) ISOURCE = 0.5mA
ISOURCE = 5mA
Output Voltage, Low, Either
Output Pin (Referred to V–)
No Load
ISINK = 0.5mA
ISINK = 5mA
AVOL Large-Signal Voltage Gain RLOAD = 10k, 0.5V < VOUT < 4.5V
● –24
● –200
●
●
● 110
1
1
120
1
–25
–220
1
27
210
110 120
32
240
mV
mV
mV
mV
mV
mV
dB
60812f
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5 Page 
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LTC6081/LTC6082
APPLICATIONS INFORMATION
Preserving Input Precision
Preserving input accuracy of the LTC6081/LTC6082 re-
quires that the application circuit and PC board layout do
not introduce errors comparable or greater than the 5μV
typical offset of the amplifiers. Temperature differentials
across the input connections can generate thermocouple
voltages of 10’s of microvolts so the connections to the
input leads should be short, close together and away from
heat dissipating components. Air current across the board
can also generate temperature differentials.
The extremely low input bias currents (0.1pA typical) al-
low high accuracy to be maintained with high impedance
sources and feedback resistors. Leakage currents on the
PC board can be higher than the input bias current. For
example, 10GΩ of leakage between a 5V supply lead and
an input lead will generate 500pA! Surround the input
leads with a guard ring driven to the same potential as the
input common mode voltage to avoid excessive leakage
in high impedance applications.
Capacitive Load
LTC6081/LTC6082 can drive capactive load up to 200pF in
unity gain. The capacitive load driving capability increases
as the amplifier is used in higher gain configurations. A
small series resistance between the output and the load
further increases the amount of capacitance the amplifier
can drive.
⎯S⎯H⎯D⎯N Pins
Pins 5 and 6 are used for power shutdown on the LTC6081
in the DD package. If they are floating, internal current
sources pull Pins 5 and 6 to V+ and the amplifiers operate
normally. In shutdown, the amplifier output is high imped-
ance, and each amplifier draws less than 2μA current.
Rail-to-Rail Input
The input stage of LTC6081/LTC6082 combines both PMOS
and NMOS differential pairs, extending its input common
mode voltage range to both positive and negative supply
voltages. At high input common mode range, the NMOS
pair is on. At low common mode range, the PMOS pair is
on. The transition happens when the common voltage is
between 1.3V and 0.9V below the positive supply. LTC6081
has better low frequency noise performance with PMOS
input on due to its lower flicker noise (see Voltage Noise
vs Frequency and 0.1Hz to 10Hz Input Voltage Noise in
Typical Performance Characteristics).
Thermal Hysteresis
Figure 1 shows the input offset voltage hysteresis of the
LTC6081IMS8 for 3 thermal cycles from –45°C to 90°C.
The typical offset shift is ±4μV. The data was taken with
the ICs in stress free sockets. Mounting to PC boards
may cause additional hysteresis due to mechanical stress.
The LTC6081 will meet offset voltage specifications in the
electrical characteristics table even after 15μV of additional
error from thermal hysteresis.
0.30
VOS CHANGE AFTER 3 THERMAL CYCLES
0.25
VVC+M=
= 0.5V
3V
300 UNITS
0.20
0.15
0.10
0.5
0
–15 –12 –9 –6 –3 0 3 6
VOS CHANGE (μV)
9 12 15
60812 F01
Figure 1. VOS Thermal Hysteresis of LTC6081MS8
60812f
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11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet LTC6082.PDF ] | |
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