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PDF TMP90C400 Data sheet ( Hoja de datos )
| Número de pieza | TMP90C400 | |
| Descripción | (TMP90C400 / TMP90C401) CMOS 8-bit Microcontrollers | |
| Fabricantes | Toshiba | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de TMP90C400 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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TOSHIBA
TLCS-90 Series
TMP90C400/401
CMOS 8–Bit Microcontrollers
TMP90C400N/TMP90C401N
TMP90C400F/TMP90C401F
1. Outline and Characteristics
The TMP90C400 is a high-speed advanced 8-bit microcontroller
applicable to a variety of equipment.
With its 8-bit CPU, ROM, RAM, timer/event counter and gen-
eral-purpose serial interface integrated into a single CMOS chip,
the TMP90C400 allows the expansion of external
memories for programs and data (up to 60K bytes). The
TMP90C401 is the same as the TMP90C400 but without
ROM.
The TMP90C400N/401N is in a shrink Dual Inline Package
(SDIP64-P-750).
The TMP90C400F/401F is in a Quad Flat package
(QFP64-P-1420A)
The characteristics of the TMP90C400 include:
(1) Powerful instructions: 163 basic instructions, including
Multiplication, division, 16-bit arithmetic operations, bit
manipulation instructions
(2) Minimum instruction executing time: 320ns (at
12.5MHz oscillation frequency)
(3) Internal ROM: 4K bytes (The TMP90C401 does not
have a built-in ROM)
(4) Internal RAM:
128 bytes
(5) Memory expansion
External memory:
60K bytes
(6) General-purpose serial interface (1 channel)
Asynchronous mode, I/O interface mode
(7) 8-bit timers (4 channel): (2 external clock inputs)
(8) Port with zero-cross detection circuit (4 inputs)
(9) Input/Output ports (56 pins)
- Ports with programmable pull-up resistor (22 pins)
- Allows I/O selection on bit basis
- Multiplexer ports of address data bus
(10) Interrupt function: 7 internal interrupts and 3 external
interrupts
(11) Micro Direct Memory Access (DMA) function (8 channels)
(12) Standby function (4 HALT modes)
The information contained here is subject to change without notice.
The information contained herein is presented only as guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties
which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. These TOSHIBA products are intended for usage in general electronic
equipments (office equipment, communication equipment, measuring equipment, domestic electrification, etc.) Please make sure that you consult with us before you use these TOSHIBA products in equip-
ments which require high quality and/or reliability, and in equipments which could have major impact to the welfare of human life (atomic energy control, spaceship, traffic signal, combustion control, all types
of safety devices, etc.). TOSHIBA cannot accept liability to any damage which may occur in case these TOSHIBA products were used in the mentioned equipments without prior consultation with TOSHIBA.
TOSHIBA CORPORATION
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2.2 Pin Names and Functions
TMP90C400/401
The names of input/output pins and their functions are summa-
rized in Table 2.2.
Pin Name
P00 ~ P07
/AD0 ~ AD7
P10 ~ P17
/A8 ~ A15
P20 ~ P23
P24
/NMI
P25
/WAIT
P26
/RD
P27
/WR
P30
/INTO
P31
/INT1
P32
/TI0
No. of pins
8
8
4
1
1
1
1
1
1
1
Table 2.2 Pin Names and Functions (1/2)
I/O 3 states
I/O
3 states
I/O
Output
I/O
I/O
Input
Function
Port 0: 8-bit I/O port that allows selection of input/output on byte basis
Address/Data bus: Functions as 8-bit bidirectional address/data bus for external memory (For 401, fixed to
address/data bus)
Port 1: 8-bit I/O port that allows selection on byte basis
Address bus: Functions as address bus (upper 8 bits) by EXT1 set for external memory (For 401, fixed to
address bus
Port 20 ~ 23: 4-bit I/O port with a pull-up resistor that can be programmed, and allows selection of
input/output on bit basis
Port 24: 1-bit I/O port with a pull-up resistor that can be programmed, and allows selection of input/output on
bit basis
Non-maskable interrupt request pin: Falling edge interrupt register pin
I/O
Input
Output
Output
Output
Output
I/O
Input
Port 25: 1-bit I/O port with a pull-up resistor that can be programmed, and allows selection of input/output on
bit basis
Wait: Input pin for connecting slow speed memory of peripheral LSI
Port 26: 1-bit output port
Read: Generates strobe signal for reading external memory (For 401, fixed to RD)
Port 27: 1-bit output port
Write: Generates strobe signal for writing into external memory (for 401, fixed to WR)
Port 30: 1-bit I/O port with a pull-up resistor that can be programmed, and allows selection of input/output on
bit basis
Interrupt request pin 0: Interrupt request pin (Level/rising edge is programmable)
Port 31: 1-bit I/O port with a pull-up resistor that can be programmed, and allows selection of input/output on
bit basis
Input Interrupt request pin 1: Rising edge interrupt request pin
I/O
Port 32: 1-bit I/O port with a pull-up resistor that can be programmed, and allows selection of input/output on
bit basis
Input Timer input 0: Counter input pin for Timer 0
TOSHIBA CORPORATION
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TMP90C400/401
3.2 Memory Map
The TMP90C400 supports a program memory and a data
memory of up to 60K bytes.
The program and data memory may be assigned to the
address space from 0000H to FFFFH.
(1) Internal ROM
The TMP90C400 internally contains an 4K-byte ROM.
The address space from 0000H ~ 0FFFH is provided
to the ROM. The CPU starts executing a program
from 0000H by resetting.
The addresses 0010H ~ 005FH in this internal ROM area
are used for the entry area for the interrupt processing.
The TMP90C401 does not have a built-in ROM; therefore,
the address space 0000H ~ 0FFFH is used as external
memory space.
(2) Internal RAM
The TMP90C400 also contains a 128-byte RAM,
which is allocated to the address space from FF00H ~
FF7FH. The CPU allows the access to a certain RAM
area (FF00H ~ FF7FH, 128 bytes) by a short operation
code (opcode) in a “direct addressing mode”.
The addresses from FF20H to FF5FH in this RAM area
can be used as parameter area for micro DMA processing
(and for any other purposes when the micro DMA
function is not used).
(3) Internal I/O
The TMP90C400 provides a 32-byte address space as
an internal I/O area, whose addresses range from FF80H
to FF9FH. This I/O area can be accessed by the CPU
using a short opcode in the “direct addressing mode”.
Figure 3.2 is a memory map indicating the areas
accessible by the CPU in the respective addressing mode.
TOSHIBA CORPORATION
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