|
|
PDF CY7C1470V33 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1470V33 | |
| Descripción | (CY7C147xV33) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CY7C1470V33 (archivo pdf) en la parte inferior de esta página. Total 29 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
CY7C1470V33
CY7C1472V33
CY7C1474V33
72-Mbit (2M x 36/4M x 18/1M x 72)
Pipelined SRAM with NoBL™ Architecture
Features
• Pin-compatible and functionally equivalent to ZBT™
• Supports 250-MHz bus operations with zero wait states
— Available speed grades are 250, 200 and 167 MHz
• Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined
operation
• Byte Write capability
• Single 3.3V power supply
• 3.3V/2.5V I/O power supply
• Fast clock-to-output time
— 3.0 ns (for 250-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• CY7C1470V33, CY7C1472V33 available in
JEDEC-standard lead-free 100-pin TQFP, lead-free and
non-lead-free 165-ball FBGA package. CY7C1474V33
available in lead-free and non-lead-free 209 ball FBGA
package
• IEEE 1149.1 JTAG Boundary Scan compatible
• Burst capability—linear or interleaved burst order
• “ZZ” Sleep Mode option and Stop Clock option
Functional Description
The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are
3.3V, 2M x 36/4M x 18/1M x 72 Synchronous pipelined burst
SRAMs with No Bus Latency™ (NoBL™) logic, respectively.
They are designed to support unlimited true back-to-back
Read/Write operations with no wait states. The
CY7C1470V33, CY7C1472V33, and CY7C1474V33 are
equipped with the advanced (NoBL) logic required to enable
consecutive Read/Write operations with data being trans-
ferred on every clock cycle. This feature dramatically improves
the throughput of data in systems that require frequent
Write/Read transitions. The CY7C1470V33, CY7C1472V33,
and CY7C1474V33 are pin compatible and functionally equiv-
alent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which when deasserted suspends operation and extends the
previous clock cycle.
Write operations are controlled by the Byte Write Selects
(BWa–BWh for CY7C1474V33, BWa–BWd for CY7C1470V33
and BWa–BWb for CY7C1472V33) and a Write Enable (WE)
input. All writes are conducted with on-chip synchronous
self-timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
Logic Block Diagram-CY7C1470V33 (2M x 36)
A0, A1, A
MODE
CLK C
CEN
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1 D1
Q1 A1'
A0 D0 BURST Q0 A0'
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 2
ADV/LD
BWa
BWb
BWc
BWd
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
D
A
T
A
S
T
E
E
R
I
N
O
U
T
P
U
T
B
U
F
F
E
R
S
E
G
INPUT
REGISTER 1 E
INPUT
REGISTER 0 E
DQs
DQPa
DQPb
DQPc
DQPd
OE
CE1 READ LOGIC
CE2
CE3
ZZ SLEEP
CONTROL
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05289 Rev. *I
Revised June 20, 2006
[+] Feedback
1 page  
www.DataSheet4U.com
Pin Configurations (continued)
CY7C1470V33
CY7C1472V33
CY7C1474V33
209-ball FBGA (14 x 22 x 1.76 mm) Pinout
CY7C1474V33 (1M x 72)
1 2 3 4 5 6 7 8 9 10 11
A DQg DQg A CE2 A ADV/LD A CE3 A DQb DQb
B
DQg
DQg BWSc BWSg
NC
WE
A
BWSb BWSf DQb
DQb
C DQg DQg BWSh BWSd NC/576M CE1 NC BWSe BWSa DQb DQb
D DQg DQg VSS NC NC/1G OE NC NC VSS DQb DQb
E
DQPg DQPc VDDQ VDDQ
VDD
VDD
VDD
VDDQ VDDQ DQPf DQPb
F DQc DQc VSS VSS VSS NC VSS VSS VSS DQf DQf
G
DQc
DQc
VDDQ VDDQ
VDD
NC
VDD
VDDQ VDDQ
DQf
DQf
H DQc DQc VSS VSS VSS NC VSS VSS VSS DQf DQf
J
DQc
DQc
VDDQ VDDQ
VDD
NC
VDD
VDDQ VDDQ
DQf
DQf
K
NC
NC CLK NC
VSS CEN
VSS
NC
NC
NC
NC
L
DQh
DQh
VDDQ VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQa
DQa
M DQh DQh VSS VSS VSS NC VSS VSS VSS DQa DQa
N
DQh
DQh
VDDQ VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQa
DQa
P DQh DQh VSS VSS VSS ZZ VSS VSS VSS DQa DQa
R
DQPd DQPh VDDQ VDDQ
VDD
VDD
VDD
VDDQ VDDQ DQPa DQPe
T DQd DQd VSS NC NC MODE NC NC VSS DQe DQe
U DQd DQd NC/144M A
AA
A
A NC/288M DQe
DQe
V DQd DQd A A A A1 A A A DQe DQe
W DQd DQd TMS TDI A A0
A
TDO
TCK
DQe
DQe
Document #: 38-05289 Rev. *I
Page 5 of 29
[+] Feedback
5 Page 
www.DataSheet4U.com
CY7C1470V33
CY7C1472V33
CY7C1474V33
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1470V33, CY7C1472V33, and CY7C1474V33
incorporates a serial boundary scan test access port (TAP).
This port operates in accordance with IEEE Standard
1149.1-1990 but does not have the set of functions required
for full 1149.1 compliance. These functions from the IEEE
specification are excluded because their inclusion places an
added delay in the critical speed path of the SRAM. Note that
the TAP controller functions in a manner that does not conflict
with the operation of other devices using 1149.1 fully compliant
TAPs. The TAP operates using JEDEC-standard 3.3V or 2.5V
I/O logic levels.
The CY7C1470V33, CY7C1472V33, and CY7C1474V33
contains a TAP controller, instruction register, boundary scan
register, bypass register, and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter-
nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should be
left unconnected. Upon power-up, the device will come up in
a reset state which will not interfere with the operation of the
device.
TAP Controller State Diagram
1
TEST-LOGIC
RESET
0
0
RUN-TEST/
IDLE
1
SELECT
DR-SCAN
1
0
1
CAPTURE-DR
0
SHIFT-DR 0
1
EXIT1-DR
1
0
PAUSE-DR 0
1
0
EXIT2-DR
1
UPDATE-DR
10
SELECT
IR-SCAN
1
0
1
CAPTURE-IR
0
SHIFT-IR
0
1
EXIT1-IR
1
0
PAUSE-IR 0
1
0
EXIT2-IR
1
UPDATE-IR
10
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Test MODE SELECT (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) of any register.
(See Tap Controller Block Diagram.)
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See Tap Controller State Diagram.)
TAP Controller Block Diagram
0
Bypass Register
Selection
TDI Circuitry
210
Instruction Register
31 30 29 . . . 2 1 0
Selection
Circuitry
Identification Register
x . . . . . 210
Boundary Scan Register
TDO
TCK
TMS TAP CONTROLLER
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating.
At power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO ball on
the falling edge of TCK.
Document #: 38-05289 Rev. *I
Page 11 of 29
[+] Feedback
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet CY7C1470V33.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CY7C1470V33 | (CY7C147xV33) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM | Cypress Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |