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PDF EClamp2340C Data sheet ( Hoja de datos )
| Número de pieza | EClamp2340C | |
| Descripción | Emi Filter And Esd Protection | |
| Fabricantes | Semtech Corporation | |
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PROTECTION PRODUCTS - EMIClampTM
Description
The EClampTM2340C is a low pass filter array with
integrated TVS diodes. It is designed to suppress
unwanted EMI/RFI signals and provide electrostatic
discharge (ESD) protection in portable electronic
equipment. This state-of-the-art device utilizes solid-
state silicon-avalanche technology for superior clamp-
ing performance and DC electrical characteristics.
They have been optimized for protection of color
LCD panels in cellular phones and other portable
electronics.
The device consists of ten identical circuits comprised
of TVS diodes for ESD protection, and a resistor -
capacitor network for EMI/RFI filtering. A series
resistor value of 100Ω and a capacitance value of
18pF is used to achieve 20dB minimum attenuation
from 800MHz to 3GHz. Each line features two stages
of TVS diode protection. The TVS diodes provide
effective suppression of ESD voltages in excess of
15kV (air discharge) and 8kV (contact discharge) per
IEC 61000-4-2, level 4.
The device is a 25-bump, 0.5mm pitch flip chip array
with a 5x5 bump grid. It measures 2.6 x 2.6 x
0.65mm. The solder bumps have a nominal diameter
of 0.315mm.
Circuit Diagram
EClamp2340C
EMI Filter and ESD Protection
for Color LCD Interface
PRELIMINARY
Features
Flip Chip bidirectional EMI/RFI filter with
integrated ESD protection
ESD protection to IEC 61000-4-2 (ESD) Level4,
+/-15kV (air), +/-8kV (contact)
Filter performance: 20dB minimum attenuation
800MHz to 3GHz
TVS working voltage: 5V
Resistor: 100 Ohms
Input Capacitance: 18pF (VR = 2.5VDC)
Protection and filtering for ten lines
Solid-state technology
Mechanical Characteristics
JEDEC MO-211, Variation BF, 0.50 mm pitch flip
chip
Nominal Dimensions: 2.6 x 2.6 x 0.65 mm
Bump Diameter: 315+/-20 µm
Non-conductive top side coating
Marking : Mark code, lot code, orientation mark
Packaging : Tape and Reel per EIA 481
Applications
Color LCD Panel Protection
Cell Phone CCD Camera Lines
Personal Digital Assistants (PDA’s)
PIN Configuration
LOW PASS FILTER
CIN = 18pF
R = 100 Ohms
Circuit 10x
Revision 4/19/2004
5 x 5 Grid Flip Chip (Ball Side View)
1 www.semtech.com
1 page  
EClamp2340C
PROTECTION PRODUCTS - EMIClampTM
Applications Information
Printed Circuit Board Finish
A uniform board finish is critical for good assembly
yield. Two finishes that provide uniform surface coat-
ings are immersion nickel gold and organic surface
protectant (OSP). A non-uniform finish such as hot air
solder leveling (HASL) can lead to mounting problems
and should be avoided.
Stencil Design
A properly designed stencil is key to achieving ad-
equate solder volume without compromising assembly
yields. A 0.100mm to 0.200mm thick, laser cut,
electro-polished stencil with 0.330mm apertures
corners with rounded corners is recommended.
Reflow Profile
The flip chip TVS can be assembled using the reflow
requirements for IPC/JEDEC standard J-STD-020B for
Sn-Pb eutectic assembly of small body components.
During reflow, the component will self-align itself on the
pad.
Circuit Board Layout Recommendations for Suppres-
sion of ESD
Good circuit board layout is critical for the suppression
of ESD induced transients. The following guidelines are
recommended:
z Place the TVS near the input terminals or connec-
tors to restrict transient coupling.
z Minimize the path length between the TVS and the
protected line.
z Minimize all conductive loops including power and
ground loops.
z The ESD transient return path to ground should be
kept as short as possible.
z Never run critical signals near board edges.
z Use ground planes whenever possible.
PRELIMINARY
Recommended NSMD Pad and Stencil Aperture
2004 Semtech Corp.
5
www.semtech.com
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