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PDF MAX1471 Data sheet ( Hoja de datos )
| Número de pieza | MAX1471 | |
| Descripción | 3V/5V ASK/FSK Superheterodyne Receiver | |
| Fabricantes | Maxim Integrated Products | |
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19-3272; Rev 1; 3/05
315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
General Description
The MAX1471 low-power, CMOS, superheterodyne, RF
dual-channel receiver is designed to receive both ampli-
tude-shift-keyed (ASK) and frequency-shift-keyed (FSK)
data without reconfiguring the device or introducing any
time delay normally associated with changing modula-
tion schemes. The MAX1471 requires few external com-
ponents to realize a complete wireless RF digital data
receiver for the 300MHz to 450MHz ISM bands.
The MAX1471 includes all the active components
required in a superheterodyne receiver including: a low-
noise amplifier (LNA), an image-reject (IR) mixer, a fully
integrated phase-locked loop (PLL), local oscillator
(LO), 10.7MHz IF limiting amplifier with received-signal-
strength indicator (RSSI), low-noise FM demodulator,
and a 3V voltage regulator. Differential peak-detecting
data demodulators are included for both the FSK and
ASK analog baseband data recovery. The MAX1471
includes a discontinuous receive (DRX) mode for low-
power operation, which is configured through a serial
interface bus.
The MAX1471 is available in a 32-pin thin QFN package
and is specified over the automotive -40°C to +125°C
temperature range.
Applications
Automotive Remote Keyless Entry (RKE)
Tire Pressure Monitoring Systems
Garage Door Openers
Wireless Sensors
Wireless Keys
Security Systems
Medical Systems
Home Automation
Local Telemetry Systems
Features
♦ ASK and FSK Demodulated Data on Separate
Outputs
♦ Specified over Automotive -40°C to +125°C
Temperature Range
♦ Low Operating Supply Voltage Down to 2.4V
♦ On-Chip 3V Regulator for 5V Operation
♦ Low Operating Supply Current
7mA Continuous Receive Mode
1.1µA Deep-Sleep Mode
♦ Discontinuous Receive (DRX) Low-Power
Management
♦ Fast-On Startup Feature < 250µs
♦ Integrated PLL, VCO, and Loop Filter
♦ 45dB Integrated Image Rejection
♦ RF Input Sensitivity*
ASK: -114dBm
FSK: -108dBm
♦ Selectable IF BW with External Filter
♦ Programmable Through Serial User Interface
♦ RSSI Output and High Dynamic Range with AGC
*0.2% BER, 4kbps, Manchester-encoded data, 280kHz IF BW
Ordering Information
PART
TEMP RANGE PIN-PACKAGE
MAX1471ATJ
-40°C to +125°C 32 Thin QFN-EP**
**EP = Exposed pad.
Pin Configuration
TOP VIEW
32 31 30 29 28 27 26 25
DSA- 1
DSA+ 2
OPA+ 3
DFA 4
XTAL2 5
XTAL1 6
AVDD 7
LNAIN 8
MAX1471
24 DVDD
23 DGND
22 DFF
21 OPF+
20 DSF+
19 DSF-
18 PDMAXF
17 PDMINF
9 10 11 12 13 14 15 16
THIN QFN
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
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315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
Typical Operating Characteristics
(Typical Application Circuit, AVDD = DVDD = HVIN = +3.0V, fRF = 434MHz, TA = +25°C, unless otherwise noted.)
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
8.0
+125°C
+105°C
7.6 +85°C
7.2
6.8
+25°C
6.4 -40°C
6.0
2.4
2.7 3.0 3.3
SUPPLY VOLTAGE (V)
3.6
BIT-ERROR RATE
vs. AVERAGE INPUT POWER (ASK DATA)
100
280kHz IF BW
10
fRF = 434MHz
1
0.2% BER
0.1 fRF = 315MHz
0.01
-123
-121 -119 -117 -115 -113
AVERAGE INPUT POWER (dBm)
-111
8.0
7.8
7.6
7.4
7.2
7.0
6.8
6.6
6.4
6.2
6.0
300
SUPPLY CURRENT
vs. RF FREQUENCY
+125°C +105°C +85°C
+25°C
-40°C
325 350 375 400 425
RF FREQUENCY (MHz)
450
BIT-ERROR RATE
vs. AVERAGE INPUT POWER (FSK DATA)
100
280kHz IF BW
FREQUENCY DEVIATION = ±50kHz
10
fRF = 434MHz
1
0.2% BER
0.1 fRF = 315MHz
0.01
-115
-113 -110 -108
AVERAGE INPUT POWER (dBm)
-105
DEEP-SLEEP CURRENT
vs. TEMPERATURE
12
10
8
6
4
2
0
-40 -15 10 35 60 85 110
TEMPERATURE (°C)
SENSITIVITY
vs. TEMPERATURE (ASK DATA)
-102
280kHz IF BW
0.2% BER
-105
-108
-111 fRF = 434MHz
-114
-117 fRF = 315MHz
-120
-40 -15 10 35 60 85 110
TEMPERATURE (°C)
SENSITIVITY
vs. TEMPERATURE (FSK DATA)
-102
280kHz IF BW
0.2% BER
-104 FREQUENCY DEVIATION = ±50kHz
-106 fRF = 434MHz
-108
-110 fRF = 315MHz
-112
-40 -15 10 35 60 85 110
TEMPERATURE (°C)
SENSITIVITY vs. FREQUENCY
DEVIATION (FSK DATA)
-98
280kHz IF BW
-100 0.2% BER
-102
-104
-106
-108
-110
-112
1
10
FREQUENCY DEVIATION (kHz)
100
RSSI vs. RF INPUT POWER
1.6
AGC HYSTERESIS: 3dB
1.4
HIGH-GAIN MODE
1.2
1.0 AGC SWITCH
POINT
0.8
0.6
0.4
0.2
LOW-GAIN MODE
0
-130 -110 -90 -70
-50
-30
RF INPUT POWER (dBm)
-10
10
_______________________________________________________________________________________ 5
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315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
Intermediate Frequency (IF)
The IF section presents a differential 330Ω load to pro-
vide matching for the off-chip ceramic filter. It contains
five AC-coupled limiting amplifiers with a bandpass-fil-
ter-type response centered near the 10.7MHz IF fre-
quency with a 3dB bandwidth of approximately 10MHz.
For ASK data, the RSSI circuit demodulates the IF to
baseband by producing a DC output proportional to
the log of the IF signal level with a slope of approxi-
mately 16mV/dB. For FSK, the limiter output is fed into a
PLL to demodulate the IF.
FSK Demodulator
The FSK demodulator uses an integrated 10.7MHz PLL
that tracks the input RF modulation and determines the
difference between frequencies as logic-level ones and
zeros. The PLL is illustrated in Figure 1. The input to the
PLL comes from the output of the IF limiting amplifiers.
The PLL control voltage responds to changes in the fre-
quency of the input signal with a nominal gain of
2.2mV/kHz. For example, an FSK peak-to-peak devia-
tion of 50kHz generates a 110mVP-P signal on the con-
trol line. This control line is then filtered and sliced by
the FSK baseband circuitry.
The FSK demodulator PLL requires calibration to over-
come variations in process, voltage, and temperature.
For more information on calibrating the FSK demodula-
tor, see the Calibration section. The maximum calibra-
tion time is 120µs. In DRX mode, the FSK demodulator
calibration occurs automatically just before the IC
enters sleep mode.
Crystal Oscillator
The XTAL oscillator in the MAX1471 is used to generate
the local oscillator (LO) for mixing with the received sig-
nal. The XTAL oscillator frequency sets the received
signal frequency as:
fRECEIVE = (fXTAL x 32) +10.7MHz
The received image frequency at:
fIMAGE = (fXTAL x 32) -10.7MHz
is suppressed by the integrated quadrature image-
rejection circuitry.
For an input RF frequency of 315MHz, a reference fre-
quency of 9.509MHz is needed for a 10.7MHz IF fre-
quency (low-side injection is required). For an input RF
frequency of 433.92MHz, a reference frequency of
13.2256MHz is required.
The XTAL oscillator in the MAX1471 is designed to pre-
sent a capacitance of approximately 3pF between the
XTAL1 and XTAL2. If a crystal designed to oscillate
with a different load capacitance is used, the crystal is
pulled away from its stated operating frequency, intro-
ducing an error in the reference frequency. Crystals
designed to operate with higher differential load capac-
itance always pull the reference frequency higher.
In actuality, the oscillator pulls every crystal. The crys-
tal’s natural frequency is really below its specified fre-
quency, but when loaded with the specified load
capacitance, the crystal is pulled and oscillates at its
specified frequency. This pulling is already accounted
for in the specification of the load capacitance.
Additional pulling can be calculated if the electrical
parameters of the crystal are known. The frequency
pulling is given by:
fp
=
Cm
2
⎛
⎜
⎝
1
Ccase + Cload
−
Ccase
1
+ Cspec
⎞
⎟
⎠
× 106
where:
fp is the amount the crystal frequency pulled in ppm.
Cm is the motional capacitance of the crystal.
Ccase is the case capacitance.
Cspec is the specified load capacitance.
Cload is the actual load capacitance.
When the crystal is loaded as specified, i.e., Cload =
Cspec, the frequency pulling equals zero.
IF
LIMITING
AMPS
PHASE
DETECTOR
CHARGE
PUMP
LOOP
FILTER
TO FSK BASEBAND FILTER
AND DATA SLICER
10.7MHz VCO
2.2mV/kHz
Figure 1. FSK Demodulator PLL Block Diagram
______________________________________________________________________________________ 11
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| PDF Descargar | [ Datasheet MAX1471.PDF ] | |
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