PDF CY22801 Data sheet ( Hoja de datos )

Número de pieza	CY22801
Descripción	Universal Programmable Clock Generator
Fabricantes	Cypress Semiconductor
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No Preview Available ! www.DataSheet4U.com Features • Integrated phase-locked loop (PLL) • Field programmable • Input frequency range: — Crystal: 8–30 MHz — CLKIN: 1–133 MHz • Output frequency: — LVCMOS: 1–200 MHz • Low jitter, high accuracy outputs • 3.3V operation • 8-pin SOIC package Logic Block Diagram XIN/CLKIN XOUT XTAL OSC PLL CY22801 Universal Programmable Clock Generator (UPCG) Benefits • Inventory of only one device, CY22801, is needed to use in various applications • In-house programming of samples and prototype quantities is available using the CY36800 InstaClock Kit • Can customize the input and output frequencies to suit your needs • High-performance PLL tailored for multiple applications • Meets critical timing requirements in complex system designs • Enables application compatibility OUTPUT DIVIDERS CLKA CLKB CLKC Pin Configuration CY22801 8-pin SOIC XIN/CLKIN VDD NC VSS 1 2 3 4 8 XOUT 7 CLKC 6 CLKA 5 CLKB Pin Description Name XIN VDD NC VSS CLKB CLKA CLKC XOUT Pin Number Description 1 Reference Input: Crystal or External Clock 2 3.3V Voltage Supply 3 No Connect; leave this pin floating 4 Ground 5 Clock Output B 6 Clock Output A 7 Clock Output C 8 Reference Output: Connect to external crystal. When the reference is an external clock signal, this pin is not used and must be left floating. Cypress Semiconductor Corporation Document #: 001-15571 Rev. • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 10, 2007 [+] Feedback 1 page CY22801 AC Electrical Characteristics[2] Parameter fREFC fREFD fOUT DC t3 t4 t5[5] t6[6] t10 Name Reference Frequency - crystal Reference Frequency - driven Output Frequency Output Duty Cycle Rising Edge Slew Rate Falling Edge Slew Rate Skew Clock Jitter PLL Lock Time Description Duty Cycle is defined in Figure 3, 50% of VDD Output Clock Rise Time, 20% - 80% of VDD Output Clock Fall Time, 80% - 20% of VDD Output-output skew between related outputs Peak-to-peak period jitter Min 8 1 1 45 0.8 0.8 – – – Typ Max Unit – 30 MHz – 133 MHz – 200 MHz 50 55 % 1.4 – V/ns 1.4 – V/ns – 250 ps 250 – ps – 3 ms Test Circuit Figure 2. Test Circuit Diagram VDD 0.1 μF OUTPUTS CLKout CLOAD Timing Definitions Figure 3. Duty Cycle Definition; DC = t2/t1 t1 t2 CLK 50% 50% GND Figure 4. Rise and Fall Time Definitions t3 t4 80% CLK 20% Notes 5. Skew value guaranteed when outputs are generated from the same divider bank. 6. Jitter measurement may vary. Actual jitter is dependent on input jitter and edge rate, number of active outputs, input and output frequencies, supply voltage, temperature, and output load. For more information, refer to the application note, Jitter in PLL-based Systems: Causes, Effects, and Solutions. Document #: 001-15571 Rev. Page 5 of 7 [+] Feedback 5 Page

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