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PDF CY22050 Data sheet ( Hoja de datos )
| Número de pieza | CY22050 | |
| Descripción | One-PLL General Purpose Flash Programmable Clock Generator | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY22050
One-PLL General Purpose
Flash Programmable Clock Generator
Features
• Integrated phase-locked loop (PLL)
• Commercial and Industrial operation
• Flash-programmable
• Field-programmable
• Low-skew, low-jitter, high-accuracy outputs
• 3.3V operation with 2.5V output option
• 16-lead TSSOP
Benefits
Internal PLL to generate six outputs up to 200 MHz. Able to generate
custom frequencies from an external reference crystal or a driven source.
Performance guaranteed for applications that require an extended temper-
ature range.
Reprogrammable technology allows easy customization, quick turnaround
on design changes and product performance enhancements, and better
inventory control. Parts can be reprogrammed up to 100 times, reducing
inventory of custom parts and providing an easy method for upgrading
existing designs.
In-house programming of samples and prototype quantities is available
using the CY3672 FTG Development Kit. Production quantities are
available through Cypress’s value-added distribution partners or by using
third party programmers from BP Microsystems, HiLo Systems, and
others.
High performance suited for commercial, industrial, networking, telecomm
and other general-purpose applications.
Application compatibility in standard and low-power systems.
Industry standard packaging saves on board space.
Part Number
CY22050FC
CY22050FI
Outputs
6
6
Input Frequency Range
8 MHz–30 MHz (external crystal)
1 MHz–133 MHz (driven clock)
8 MHz–30 MHz (external crystal)
1 MHz–133 MHz (driven clock)
Output Frequency Range
80 kHz–200 MHz (3.3V)
80 KHz–166.6 MHz (2.5V)
80 kHz–166.6 MHz (3.3V)
80 KHz–150 MHz (2.5V)
Specifications
Field-programmable
commercial temperature
Field-programmable
industrial temperature
Logic Block Diagram
XIN
XOUT
OSC.
QΦ
VCO
P
PLL
Divider
Bank 1
Divider
Bank 2
Output
Select
Matrix
LCLK1
LCLK2
LCLK3
LCLK4
CLK5
CLK6
OE
Pin Configuration
VDD AVDD AVSS VSS VDDL VSSL PWRDWN
XIN
VDD
AVDD
PWRDWN
AVSS
VSSL
LCLK1
LCLK2
1
2
3
4
5
6
7
8
16 XOUT
15 CLK6
14 CLK5
13 VSS
12 LCLK4
11 VDDL
10 OE
9 LCLK3
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07006 Rev. *D
Revised January 29, 2005
1 page  
CY22050
DC Electrical Characteristics
Parameter[4]
Name
IOH3.3
IOL3.3
IOH2.5
IOL2.5
VIH
VIL
IVDD[5,6]
IVDDL3.3[5,6]
IVDDL2.5[5,6]
IDDS
IOHZ
IOLZ
Output High Current
Output Low Current
Output High Current
Output Low Current
Input High Voltage
Input Low Voltage
Supply Current
Supply Current
Supply Current
Power-Down Current
Output Leakage
Description
VOH = VDD – 0.5V, VDD/VDDL = 3.3V
VOL = 0.5V, VDD/VDDL = 3.3V
VOH = VDDL – 0.5V, VDDL = 2.5V
VOL = 0.5V, VDDL = 2.5V
CMOS levels, 70% of VDD
CMOS levels, 30% of VDD
AVDD/VDD Current
VDDL Current (VDDL = 3.465V)
VDDL Current (VDDL = 2.625V)
VDD = VDDL = AVDD = 3.465V
VDD = VDDL = AVDD = 3.465V
Min.
12
12
8
8
0.7
0
Typ.
24
24
16
16
45
25
17
Max.
1.0
0.3
50
10
Unit
mA
mA
mA
mA
VDD
VDD
mA
mA
mA
µA
µA
AC Electrical Characteristics
Parameter[4]
Name
Description
Min.
Typ. Max. Unit
t1 Output frequency, Clock output limit, 3.3V
commercial temp Clock output limit, 2.5V
0.08 (80 kHz)
0.08 (80 kHz)
200
166.6
MHz
MHz
Output frequency, Clock output limit, 3.3V
industrial temp
Clock output limit, 2.5V
0.08 (80 kHz)
0.08 (80 kHz)
166.6
150
MHz
MHz
t2 Output duty cycle Duty cycle is defined in Figure 2; t1/t2
fOUT > 166 MHz, 50% of VDD
Duty cycle is defined in Figure 2; t1/t2
fOUT < 166 MHz, 50% of VDD
t3LO Rising edge slew Output clock rise time, 20% – 80% of VDDL.
rate (VDDL = 2.5V) Defined in Figure 3
t4LO Falling edge slew Output clock fall time, 80% – 20% of VDDL.
rate (VDDL = 2.5V) Defined in Figure 3
t3HI Rising edge slew Output clock rise time, 20% – 80% of
rate (VDDL = 3.3V) VDD/VDDL. Defined in Figure 3
t4HI Falling edge slew Output clock fall time, 80% – 20% of
rate (VDDL = 3.3V) VDD/VDDL. Defined in Figure 3
t5[7] Skew
Output-output skew between related outputs
t6[8] Clock jitter
Peak-to-peak period jitter (see Figure 4)
40
45
0.6
0.6
0.8
0.8
50 60
%
50 55
%
1.2 V/ns
1.2 V/ns
1.4 V/ns
1.4 V/ns
250
250
ps
ps
t10 PLL lock time
0.30 3
ms
Notes:
4. Not 100% tested, guaranteed by design.
5. IVDD currents specified for two CLK outputs running at 125 MHz, two LCLK outputs running at 80 MHz, and two LCLK outputs running at 66.6 MHz.
6. Use CyClocksRT to calculate actual IVDD and IVDDL for specific output frequency configurations.
7. Skew value guaranteed when outputs are generated from the same divider bank. See Logic Block Diagram for more information.
8.
Jitter measurement will vary. Actual jitter is dependent on XIN jitter and edge rate, number
and output load. For more information, refer to the application note, “Jitter in PLL-based
oSfyasctteivmeso: uCtpauutsse,so,uEtpffuetcftrse,qaunedncSieoslu,tVioDnDsL,”(2a.v5aVilaobr l3e.3aVt )h,tttepm://pwewrawt.ucrye-,
press.com, or contact your local Cypress Field Applications Engineer.
Document #: 38-07006 Rev. *D
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