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PDF LNK564 Data sheet ( Hoja de datos )
| Número de pieza | LNK564 | |
| Descripción | (LNK562 - LNK564) Energy Effi cient Off-Line Switcher IC | |
| Fabricantes | Power Integrations | |
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www.DataSheet4U.com
LNK562-564
LinkSwitch®-LP
Energy Efficient Off-Line Switcher IC for
Linear Transformer Replacement
Product Highlights
Lowest System Cost and Advanced Safety Features
• Lowest component count switcher
• Very tight parameter tolerances using proprietary IC
trimming technology and transformer construction
techniques enable Clampless™designs – decreases
component count/system cost and increases efficiency
• Meets industry standard requirements for thermal overload
protection – eliminates the thermal fuse used with linear
transformers or additional components in RCC designs
• Frequency jittering greatly reduces EMI – enables low cost
input filter configuration
• Meets HV creepage requirements between DRAIN and all
other pins, both on the PCB and at the package
• Proprietary E-Shield™ transformer eliminates Y capacitor
Superior Performance over Linear and RCC
• Hysteretic thermal shutdown protection – automatic
recovery improves field reliability
• Universal input range allows worldwide operation
• Auto-restart reduces delivered power by >85% during
short circuit and open loop fault conditions
• Simple ON/OFF control, no loop compensation needed
• High bandwidth provides fast turn on with no overshoot
and excellent transient load response
EcoSmart®– Energy Efficiency Technology
• Easily meets all global energy efficiency regulations with
no added components
• No-load consumption <150 mW at 265 VAC input
• ON/OFF control provides constant efficiency to very
light loads – ideal for mandatory CEC regulations
Applications
• Chargers for cell/cordless phones, PDAs, power tools,
MP3/portable audio devices, shavers etc.
• Standby and auxiliary supplies
Description
LinkSwitch-LP switcher ICs cost effectively replace all
unregulated isolated linear transformer based (50/60 Hz) power
supplies up to 3 W output power. For worldwide operation, a
single universal input design replaces multiple linear transformer
based designs. The self-biased circuit achieves an extremely low
no-load consumption of under 150 mW. The internal oscillator
AC
IN
+ DC
Output
LinkSwitch-LP
D
FB
BP
S
(a) PI-3923-092705
VO
Rated Output Power = VR • IR
VR
IR IO
(b) PI-3924-011706
Figure 1. Typical Application – not a Simplified Circuit (a) and
Output Characteristic Envelope (b).
OUTPUT POWER TABLE1
230 VAC ±15%
85-265 VAC
PRODUCT4
Adapter2
Open
Frame3
Adapter2
Open
Frame3
LNK562P or G 1.9 W 1.9 W 1.9 W 1.9 W
LNK563P or G 2.5 W
LNK564P or G 3 W
2.5 W
3W
2.5 W 2.5 W
3W 3W
Table 1. Notes: 1. Output power may be limited by specific application
parameters including core size and Clampless operation (see Key
Application Considerations). 2. Minimum continuous power in a typical
non-ventilated enclosed adapter measured at 50 °C ambient. 3. Minimum
practical continuous power in an open frame design with adequate
heat sinking, measured at 50 °C ambient. 4. Packages: P: DIP-8B,
G: SMD-8B. For lead-free package options, see Part Ordering
Information.
frequency is jittered to significantly reduce both quasi-peak and
average EMI, minimizing filter cost.
October 2005
1 page  
www.DataSheet4U.com
Key Application Considerations
Output Power Table
The data sheet maximum output power table (Table 1) represents
the maximum practical continuous output power level that can
be obtained under the following assumed conditions:
1. The minimum DC input voltage is 90 V or higher for 85 VAC
input, or 240 V or higher for 230 VAC input or 115 VAC
with a voltage doubler. The value of the input capacitance
should be large enough to meet these criteria for AC input
designs.
2. Secondary output of 6 V with a Schottky rectifier diode.
3. Assumed efficiency of 70%.
4. Voltage only output (no secondary-side constant current
circuit).
5. Discontinuous mode operation (KP > 1).
6. A suitably sized core to allow a practical transformer design
(see Table 2).
7. The part is board mounted with SOURCE pins soldered
to a sufficient area of copper to keep the SOURCE pin
temperature at or below 100 °C.
8. Ambient temperature of 50 °C for open frame designs
and an internal enclosure temperature of 60 °C for adapter
designs.
Core Size
EE13
EE16
EE19
LinkSwitch-LP Device
LNK562 LNK563 LNK564
1.1 W
1.4 W
1.7 W
1.3 W
1.7 W
2W
1.9 W
2.5 W
3W
Table 2. Estimate of Transformer Power Capability vs.
LinkSwitch-LP Device and Core Size at a Flux Density of
1500 Gauss (150 mT).
Below a value of 1, KP is the ratio of ripple to peak primary
current. Above a value of 1, KP is the ratio of primary MOSFET
OFF time to the secondary diode conduction time. Due to
the flux density requirements described below, typically a
LinkSwitch-LP design will be discontinuous, which also has
the benefit of allowing lower-cost fast (vs. ultra-fast) output
diodes and reducing EMI.
Clampless Designs
Clampless designs rely solely on the drain node capacitance
to limit the leakage inductance induced peak drain-to-source
voltage. Therefore the maximum AC input line voltage, the
value of VOR, the leakage inductance energy, (a function of
leakage inductance and peak primary current), and the primary
winding capacitance determine the peak drain voltage. With no
significant dissipative element present, as is the case with an
external clamp, the longer duration of the leakage inductance
ringing can increase EMI.
LNK562-564
The following requirements are recommended for a universal
input or 230 VAC only Clampless design:
1. Clampless designs should only be used for PO ≤ 2.5 W using
a
V
OR
of
≤
90
V
2. For designs with PO ≤ 2 W, a two-layer primary must be
used to ensure adequate primary intra-winding capacitance
in the range of 25 pF to 50 pF.
3. For designs with 2 < PO ≤ 2.5 W, a bias winding must be added
to the transformer using a standard recovery rectifier diode
(1N4003– 1N4007) to act as a clamp. This bias winding may
also be used to externally power the device by connecting
a resistor from the bias winding capacitor to the BYPASS
pin. This inhibits the internal high voltage current source,
reducing device dissipation and no-load consumption.
4. For designs with PO > 2.5 W, Clampless designs are not
practical and an external RCD or Zener clamp should be
used.
5. Ensure that worst-case, high line, peak drain voltage is below
the BVDSS specification of the internal MOSFET and ideally
≤ 650 V to allow margin for design variation.
V (Reflected Output Voltage), is the secondary output plus
OR
output diode forward voltage drop that is reflected to the
primary via the turns ratio of the transformer during the diode
conduction time. The VOR adds to the DC bus voltage and the
leakage spike to determine the peak drain voltage.
Audible Noise
The cycle skipping mode of operation used in LinkSwitch-LP
can generate audio frequency components in the transformer.
To limit this audible noise generation, the transformer should
be designed such that the peak core flux density is below
1500 Gauss (150 mT). Following this guideline and using the
standard transformer production technique of dip varnishing,
practically eliminates audible noise. Vacuum impregnation
of the transformer is not recommended, as it does not provide
any better reduction of audible noise than dip varnishing. And
although vacuum impregnation has the benefit of increased
transformer capacitance (which helps in Clampless designs),
it can also upset the mechanical design of the transformer,
especially if shield windings are used. Higher flux densities are
possible, increasing the power capability of the transformers
above what is shown in Table 2. However careful evaluation of
the audible noise performance should be made using production
transformer samples before approving the design.
Ceramic capacitors that use dielectrics such as Z5U, when used
in clamp circuits, may also generate audio noise. If this is the
case, try replacing them with a capacitor having a different
dielectric or construction, for example a film type.
Bias Winding Feedback
To give the best output regulation in bias winding designs, a
slow diode such as the 1N400x series should be used as the
5F
10/05
5 Page 
www.DataSheet4U.com
LNK562-564
S1
50 V
470 Ω
5W
D FB
BP
SS
SS
470 kΩ
0.1 µF
S2
50 V
Figure 7. General Test Circuit.
Figure 8. Duty Cycle Measurement.
DCMAX
(internal signal)
tP
FB
VDRAIN
1
t=
P fOSC
tEN
Figure 9. Output Enable Timing.
PI-3490-060204
PI-3707-112503
100
0
-100
2 µs
Time (µs)
Figure 10. Peak Negative Pulsed DRAIN Current
Waveform.
11F
10/05
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet LNK564.PDF ] | |
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